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From: firth@sei.cmu.edu (Robert Firth)
Newsgroups: comp.arch,rec.arts.sf-lovers,alt.cyberpunk
Subject: Re: Count Zero Interrupt
Message-ID: <9438@fy.sei.cmu.edu>
Date: 7 Nov 90 16:27:25 GMT
References: <1427@carol.fwi.uva.nl> <4bC2VW600VIE094FUA@andrew.cmu.edu>
Reply-To: firth@sei.cmu.edu (Robert Firth)
Organization: Software Engineering Institute, Pittsburgh, PA
Lines: 17

In article <4bC2VW600VIE094FUA@andrew.cmu.edu> mg20+@andrew.cmu.edu (Michael Paul Greelish) writes:

>Count Zero Interrupt:

>If there is an interrupt, reset the counter (register) to zero.

This feature also exists in several varieties of peripheral
device controller, for instance the PDP-11 programmable clock
(KW-11P of happy memory) has a 16-bit decrementing counter.

However, the meaning is the reverse of Michael's statement:
when the counter reaches zero, generate an interrupt.

In this case, the interrupt signals the end of a programmed
interval of time; in other cases, for instance an interrupt
from a data transfer device, it might signal completion of a
multi-byte (or whatever) transfer.