Path: utzoo!utgpu!cunews!cognos!alzabo!andras
From: andras@alzabo.uucp (Andras Kovacs)
Newsgroups: comp.arch
Subject: Re: The CPU with 3 brains
Message-ID: <1990Nov6.172727.15348@alzabo.uucp>
Date: 6 Nov 90 17:27:27 GMT
References: <42737@mips.mips.COM> <PCG.90Nov4183157@athene.cs.aber.ac.uk>
Reply-To: andras@alzabo.UUCP (Andras Kovacs)
Organization: Brian's XENIXlings, Ottawa, Canada
Lines: 23


    I would like to invite everyone to read the "IBM Research Journal"
describing the POWER architecture (what a name, eh? Performance Optimization
With Enhanched RISC - the prototype's codename was AMERICA).
    Anyway, I enjoyed the hardware overview of the chip very much. Previously
I thought that "this must be an over-engineered chip if they used 6 million
transistors". But after reading about it, I feel that the RISC 6000 is a true
state-of-the art chip which incorporates the latest research technology.
(I am not an EE, sadly).
    So I am not convinced that the right thing is to put multiple processors
on the same die. I believe the solution will be some very fast VLIW chip
with minimum instruction set which will be able to emulate all today's CISC
chips (and probably RISC ones as well) at a reasonable speed. My 4 MIPS ARM
can emulate an 8086 + the PC hardware (which is a bitch) at a ratio of 1.4
to the original 4.77 MHz IBM PC. Apparently the (roughly) 12 MIPS ARM3 can
emulate at the speed of a PC AT (even at the original 6 MHz, that's not bad
for me). So I expect that a 100-150-200+ MIPS VLIW MISC chip could do a
beautiful job of emulating ANY of today's chips at a reasonable rate.

This was my $0.02's worth :-)
-- 
Andras Kovacs
andras@alzabo.UUCP