Path: utzoo!attcan!uunet!ogicse!ucsd!sdcc6!ga1056
From: ga1056@sdcc6.ucsd.edu (Dau-Tsuong)
Newsgroups: comp.arch
Subject: Re: Optical Computers
Message-ID: <13960@sdcc6.ucsd.edu>
Date: 7 Nov 90 01:08:44 GMT
References: <5506.9011011201@olympus.cs.hull.ac.uk>
Organization: University of California, San Diego
Lines: 61

We at university of California at San Diego share Alan Huang's
enthusiasm on optical computing.  We have an Optical Information
Processing Group here that is actively pursuing optoelectronic
devices, systems, and architectures.  Besides AT&T and us, several
other universities are also working on similar systems, CalTech, MIT,
Stanford, U of Colorado, USC, just a few names on the top of stack
now.  Many publications in this area has been published in Applied
Optics and Optical Engineering.

Our work at UCSD is primarily using holographic optics to
interconection VLSI processing elements.  Based on power and speed
considerations, optical interconnection is better than electronic when
the interconnect distance is above 1mm (assuming some operating
parameters I cannot recall right away.  Let me know if you want more
detail).  So it appears to us that the best architecture is an array
of fine-grain electronic processing elements (PE) that are optically
connected together, we call it Programmable Optoelectronic
Multiprocessor, i.e. POEM.  This is a SIMD architecture.  The
prototype POEM we are working on has 4 1-bit CPU's on each plane.  Two
such processor planes are optically interconnected by two computer
generated holograms (CGH).  Each PE has a spatial light modulator and
three optical dectors.  There are no interconnection between the PEs
on the same plane, so optical I/O is rather important.  Work is also
in progress to use photorefractive crystals (PRC) to store several
interconnection patterns and multiplex them using a phase code.  In
the near future, we should expect to see dynamically reconfigurable
interconnections using these crystals.  This week, the Optical Society
of America is holding its annual meeting in Boston.  There are several
presentations on high speed backplane interconnection using optical
technology.

Comparing to purely electronic multiprocessing systems, our approach
differs mostly in decoupling the processing and the interconnection.
The interconenction wires doesn't compete for the same silicon area on
a wafer.  Besides, laser beam don't have the capacitive effects at
increased distance. POEM is able to implement most of the
interconnection network you can think of: butterfly, shuffle, etc and
also the irregular interconnections such as expander graphs (used in
the O(log n) optimal sorting network of Ajtai, Komlos, and Smezeredi).
We have recently build a VHDL model using Vantage VHDL compiler.  It
accurately models the optoelectronic device characteristics and of
course the CMOS processing element with 64 bit memory.  You might
think 2 x 4 such processors cannot do anything siginificant, yes you
are right.  But we are planning to scale this up.  The dream is
1024x1024 (1Meg PEs on each plane) but I'll be very happy to see 32x32
before I get my PhD.  The limitation now is the yield and speed of good
spatial light modulators that gives optical binary signals.

This is a rather brief summary.  I can send you dozens of papers if
you are interested. I'd like to see more discussion on this topic.  I
have implemented a simple demo to search and project 8 records in
parallel, the execution time would stay constant whe the array is
scaled up to any size.  I'd suppose we will hit the bottleneck of the
sequential host computer first.


George D.-T. Lu
UCSD OIPG
lu@poet.ucsd.edu
dlu@ucsd.edu
dlu@ucsd.bitnet
ucsd!dlu