Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!wuarchive!emory!att!bu.edu!purdue!mentor.cc.purdue.edu!l.cc.purdue.edu!cik
From: cik@l.cc.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: The CPU with 3 brains
Summary: Or lots of instructions
Message-ID: <2722@l.cc.purdue.edu>
Date: 8 Nov 90 13:08:58 GMT
References: <42737@mips.mips.COM>
Organization: Purdue University Statistics Department
Lines: 25

In article <42737@mips.mips.COM>, mark@mips.COM (Mark G. Johnson) writes:

			....................

|        SPARC CPU:   30K gates   }     all of these reside on the
|        MIPS CPU:    30K gates   }     same die, a 100K gate array
|        i286 CPU:    30K gates   }     in BiCMOS technology
 
> If this chip were finished, complete, debugged, and available today,
> imagine the cool things you could do with it.  Also imagine the
> Budzillions of dollars' worth of software already written for your
> machine.  Also imagine the frolic and fun of porting the O/S's and
> other system software onto this three-brained, schizophrenic machine.
> "An excellent source of thesis topics," as they say at 6100 Main in
> Houston.

So you would have 3 highly limited CPUs with largely similar capabilities.
Big deal.  Or by intelligently designing the operations so that different
operations could use the same gates, you could get most, if not all, of
the operations suggested by posters to this net, as well as other things
which can be done quickly in hardware but are slow in software.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)