Path: utzoo!utgpu!watserv1!ria!uwovax!brent From: brent@uwovax.uwo.ca (Brent Sterner) Newsgroups: comp.arch Subject: Re: The CPU with 3 brains Message-ID: <7692.27393066@uwovax.uwo.ca> Date: 8 Nov 90 15:16:06 GMT References: <42737@mips.mips.COM> <2722@l.cc.purdue.edu> Organization: CCS, U. of Western Ontario Lines: 27 In article <2722@l.cc.purdue.edu>, cik@l.cc.purdue.edu (Herman Rubin) writes: > In article <42737@mips.mips.COM>, mark@mips.COM (Mark G. Johnson) writes: > > .................... > > | SPARC CPU: 30K gates } all of these reside on the > | MIPS CPU: 30K gates } same die, a 100K gate array > | i286 CPU: 30K gates } in BiCMOS technology Sorry if this has been suggested before, but why not: 3 of SPARC CPU: 30K gates or 3 of MIPS CPU: 30K gates or 3 of i286 CPU: 30K gates ie, 3 different dies. Integrate each with a symmetric multi-processing os (ooops, my s/w background is showing :-) to really exploit the capacity of the chip. Most people I know have a favourite system, and do *not* switch among systems like the above (necessity excepted). Could be a screamer in a ws environment, provided you could handle the io. -- Brent Sterner Technical Support Manager, Academic Systems Fast: <129.100.2.13> Telephone (519)661-2151 x6036 Slow: Computing & Communications Services, Natural Sciences Building The University of Western Ontario, London, Ontario, Canada N6A 5B7