Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!caen!shorty.engin.umich.edu!milamber
From: milamber@caen.engin.umich.edu (Daryl Scott Cantrell)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: RISC Amiga WHat's RISC?
Message-ID: <1990Nov9.222501.21238@engin.umich.edu>
Date: 9 Nov 90 22:25:01 GMT
References: <39367@ut-emx.uucp> <15759@cbmvax.commodore.com> <yorkw.658182081@pasture.ecn.purdue.edu>
Sender: news@engin.umich.edu (CAEN Netnews)
Organization: University of Michigan Engineering, Ann Arbor
Lines: 39

In article <yorkw.658182081@pasture.ecn.purdue.edu> yorkw@pasture.ecn.purdue.edu (Willis F York) writes:
>I know RISC means Reduced INstruction Set Computer (Or Close)
[...]
>But what does this mean?

  RISC == Reduced Instruction Set Computing.  It is sort of a different way of
thinking about how computing should be done.. A "normal" computer like an Amiga
is a CISC computer (Complex ISC).  It's CPU, the 680x0, has instructions to do
all sorts of high-level things, like multiplying two signed numbers, allocating
a frame on a private stack, or packing BCDs.  Many of these comlex instructions
take several "cycles" of the processor.  This is why an A3000 clocked at 25 MHz
does not actually perform 25 million instructions per second (MIPS).  A RISC
processor, on the other hand, seeks to do away with any instruction that can't
be done entirely in one cycle, unless it's absolutely necessary.  Complex oper-
ations are implemented as routines which are built from the simple, FAST in-
structions.  They generally take on the order of 1.2-1.4 cycles per instruc-
tion.  And many also try to perform more than one instruction at a time.

----
Exit(TEACHERMODE);
Begin(OPINION);
----

  Of course, RISC will never really be that much faster than CISC because CISC
chips can always bail out.. By pipelining their architecture for the "most-
used" instructions that RISC chips implement, and still having the higher-
level functions available as microcode, which would be much slower than the
optimized instructions but still faster than RISC implementations.  Motorola
seems to be doing exactly this with the 68040, I've seen 1.2-1.3 cyc/ins all
over the place..

>yorkw@ecn.purdue.edu  Willis F York    


+---------------------------------------+----------------------------+
|   // Daryl S. Cantrell                |   These opinions are       |
| |\\\ milamber@caen.engin.umich.edu    |    shared by all of    //  |
| |//  HELP! HELP! I'm being REPRESSED! |        Humanity.     \X/   |
+---------------------------------------+----------------------------+