Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!aplcen!haven!udel!rochester!cornell!johnhlee From: johnhlee@flute.cs.cornell.edu (John H. Lee) Newsgroups: comp.sys.amiga.tech Subject: Re: Static vs. static column vs. dynamic vs. ??? Message-ID: <48149@cornell.UUCP> Date: 9 Nov 90 20:07:11 GMT References: <15571@brahms.udel.edu> Sender: nobody@cornell.UUCP Reply-To: johnhlee@cs.cornell.edu (John H. Lee) Distribution: na Organization: Cornell Univ. CS Dept, Ithaca NY Lines: 76 Summary: Followup-To: In article <15571@brahms.udel.edu> don@brahms.udel.edu (Donald R Lloyd) writes: > Questions: > Why is DRAM slower than SRAM? I can't see how having to > refresh it would cause any tremendous slowdown. Two things: DRAM design and refresh. RAMs are arranged in a matrix with memory cells set in rows, each row sharing the same sense line. The capacitance of the sense line is non-significant. In a SRAM, each memory cell actively drives its sense line, so access is fast, but the cell is large as it requires at least 4 transistors (to form a flip-flop.) In a DRAM, each memory cell is a capacitor and a gate transistor with only the stored charged in the miniscule capacitor driving the sense line, so access is slower, but each cell can be made much smaller. Since no capacitor is perfect, periodic refresh cycles are needed to recharge the capacitors and the refresh cycles times are comparable to a normal access. A DRAM also requires a "recovery period" call pre-charge that ensures that the amps on the sense lines can detect the miniscule capacitor charges. This period is on the order of an access and is the reason why a DRAM can be accessed only half as fast as its access time. > What is static column RAM? Static column RAMs support a faster access method. A normal access requires that the address be clocked into two phases: row address with RAS (Row Address Strobe) then column address with CAS (Column Address Strobe.) Each strobe has a minimum hold time. Now a static column RAM permits both strobes to be held active and the column address to change. The RAM can provide valid data much faster since the row address is already latched and row is already accessed. > I've been told it's the same as static > RAM, but that doesn't seem right (otherwise the 3000 would be > a good bit faster and a good bit more expensive). Is it the > equivalent of what Tannenbaum calls pseudo-static? No. I believe psuedo-static RAMs only implement hidden refresh within the chip. The two concepts are not the same. > What about VRAM? Somehow specially designed for video memory, > or just some marketer's way to make the static RAM on a video > card sound superior? VRAMs are usually high speed RAMs with special features to make the video system simpler, like built-in shift registers and dual access-ports. > While I'm at it, why are ROMs inherently so slow? ROMs aren't inherently slow. However, depending on their design, ROMs may have a largely passive structure being essentially a huge, dense matrix of wires with cross-links and the capacitance of the lines affect speed. In trade journals I regularly see advertised ROMs that are as fast as high-speed RAMs. > Why is there air? Because we need something to blow the smog out of L.A. (not that it works all the time, but engineering considerations and funding impose limitations.) > How many licks does it take to get to the center of a Tootsie > Pop? Three. > Where's my free 68040 upgrade for the 3000 I just ordered? I don't know. I already got mine. :-) > Thanks for any info you can provide. You're welcome. ------------------------------------------------------------------------------- The DiskDoctor threatens the crew! Next time on AmigaDos: The Next Generation. John Lee Internet: johnhlee@cs.cornell.edu The above opinions of those of the user, and not of this machine.