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From: jackin@vehka.uta.fi (Markku M{enp{{)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Faster RAM <==> Faster operation
Message-ID: <1737@kielo.uta.fi>
Date: 5 Nov 90 15:44:14 GMT
References: <1718@kielo.uta.fi> <1990Nov4.221653.4823@xrtll.uucp>
Sender: news@uta.fi
Reply-To: jackin@vehka.uta.fi (Markku M{enp{{)
Organization: University of Tampere, Finland
Lines: 42
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In article <1990Nov4.221653.4823@xrtll.uucp> silver@xrtll.UUCP (Hi Ho Silver) writes:
>In article <1718@kielo.uta.fi> jackin@vehka.uta.fi (Markku M{enp{{) writes:
>$I am wondering about how faster ram affects perfomance.
>$I understand that non-cache boards probably benefit from
>$faster ram but is it the same with cache MBs too ?
>
>   Yes, but nowhere near as much. 
>   If 90% of your memory accesses are serviced out of the cache, and your
>main memory runs at 2 wait states (and assuming cache misses take no
>additional clock cycles of their own), your average number of wait states
>would be
>
>	.9 * 0		+ .1 * 2		= .2
>	(the cache)	(main memory)
>
>   If you reduce your main memory wait states to 1 by replacing the
>chips with faster memory, you then end up with an average of .1 wait
>states per memory access.

This is true for write-back cache method. It doesn't update main memory
if a write operation remains in cached areas. This method is used in for
example Everex machines. However the most common method is write-through 
method which *allways* updates main memory when a write operation occures. 
So if our read/write-operations go like this :

	90% hits cache 
	10% misses cache 

	.45 * 0		+ .45 * 2	+ .1 * 2 	= 1.1
	(cache/read)	(cache/write)	(main memory)	

Now if we could reduce our main memory waitstates by 1 we could get 
.55 waitstates which could give us a noticable speed increase over 1.1 ws.

The third method, posted write-through cache, is also used but I don't
know if it is very common.

Markku
--
Markku M{enp{{ 
email : jackin@vehka.uta.fi
phone : 358 31 561 575 (in Finland (931) 561 575)