Path: utzoo!attcan!uunet!lupine!rfg
From: rfg@NCD.COM (Ron Guilmette)
Newsgroups: comp.sys.intel
Subject: Re: i960CA benchmark results
Keywords: i960CA, benchmarks
Message-ID: <2464@lupine.NCD.COM>
Date: 7 Nov 90 15:51:00 GMT
References: <13912@neptune.inf.ethz.ch>
Organization: Network Computing Devices, Inc., Mt. View, CA
Lines: 59

In article <13912@neptune.inf.ethz.ch> brandis@inf.ethz.ch (Marc Brandis) writes:
>Does anybody have some benchmark results for the i960CA, especially as
>compared to other processors? I would be very interested in the integer
>SPECmarks (as the CA does not have an FPU), the Dhrystone rating,
>Hennessy-Benchmark results or similar stuff.

I seriously doubt that you will ever see SPEC numbers for the i960.
You see the programs in the SPEC suite tend to be large general
purpose programs.  I don't recall what all of them are, but I know
for sure that one of them is GCC (the GNU C compiler).  At least
that program (and probably many of the others in the SPEC suite)
ASSUME that you have something kinda like UNIX running on the system
under test.

To the best of my knowledge, UNIX hasn't been ported to the 960, nor
I believe, is it likely to be anytime soon.  After all, the 960 is
for *embedded* applications, right?

>Moreover, does anybody know how well the i960CA puts its multiple
>execution units into use? Is the Intel rating of 66 MIPS at 33 MHz 
>realistic for non-toy programs?

I believe that Intel states plainly that the 66 MIPS figure is peak
(but I'm not 100% sure).  Perhaps it was 99 MIPS peak for the CA
because of the possibility that up to three instructions could be
in three different functional units at one time.  But you can't sustain
that for any more than (perhaps) one cycle, because this (rare?)
case only happens when three out of a group of four instructions
meet certain criteria.  And then (I believe) you get to spend one
cycle (or more) executing just the one remaining instruction out
of that same group of four.

Keep in mind that this all applied only to the CA anyway (and possibly
some of the new recently announced family members).  Other family
members do not dispatch multiple instructions to multiple functional
units in the same cycle.

Regarding the general question of how well compilers (e.g. for C and
FORTRAN) schedule instructions to make use of the multiple functional
units in the CA, well... this will (of course) depend on the compiler
in question.  For the GNU C compiler the answer (for the moment) is
that instruction scheduling doesn't happen at all.  The chips (or
rather the instructions) just fall where they may.  That should change
when the long rumored GCC Version 2 appears, but that's not generally
available today.

With respect to other compilers, I have no specific information.  I can
say however that the folks at Intel are no dummies, and that they
certainly realize that instruction scheduling is a very significant
issue for i960 compilers.  I don't think it would be surprizing
(to anyone) if we all found out (later on) that they were looking
into the question of how to make their chips look better (performance-
wise) via compiler technology.

-- 

// Ron Guilmette  -  C++ Entomologist
// Internet: rfg@ncd.com      uucp: ...uunet!lupine!rfg
// Motto:  If it sticks, force it.  If it breaks, it needed replacing anyway.