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From: srm@Matrix.COM (Steve Morris)
Newsgroups: comp.sys.m68k
Subject: 68020 cache and loops
Message-ID: <1990Nov7.204723.4072@Matrix.COM>
Date: 7 Nov 90 20:47:23 GMT
Reply-To: srm@matrx.matrix.com (Steve Morris)
Organization: Matrix Corporation, Raleigh, North Carolina
Lines: 26


Some folks have claimed that

            Loop:
                ...                             ; whatever
                subq    #1,<count_reg>          ; decrement counter reg
                bne     Loop                    ; branch if not zero


is faster than

            Loop:
                ...                             ; whatever
                dbra    <count_reg>,Loop        ; branch if not -1


because the next instruction following the 'dbra' instruction
is always prefetched by the 68020 (and never cached).

Can someone shed some light on this?

-- 
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| Steve Morris                         srm@matrix.com         |
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