Path: utzoo!attcan!uunet!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.sys.m88k Subject: Re: Crystal Balls Message-ID: <42762@mips.mips.COM> Date: 5 Nov 90 17:42:25 GMT References: <1990Oct14.003906.26373@wolves.uucp> <1536@ftc.framentec.fr> <1990Oct19.120218.9450@canterbury.ac.nz> <656404917.9119@proa.sv.dg.com> <1095@dg.dg.com> <42589@mips.mips.COM> <10947@pt.cs.cmu.edu> <42609@mips.mips.COM> <1108@dg.dg.com> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 73 In article <1108@dg.dg.com> mpogue@dg-rtp.dg.com (Mike Pogue) writes: >John Mashey writes: > >> re: 85MHz R6000: huh? (The system product was originally announced at >> 67.5MHz, and that was close, if a little optimistic.l) > Let's not mix SYSTEM announcements with CHIP announcements, eh? Lindsay's >point was that the R6000 chip's original performance goal was >85Mhz clock, >when in fact, the chip (as it finally ended up) works at a clock speed about >25% lower. > John, would you care to comment on the original (announced, leaked, internal, >etc.) performance goals for the R6000? Sure. 1) There was a paper called "An 85-MHz ECL RISC Microprocessor ..." that was accepted by ISSCC for Feb 1990, but which ISSCC later cancelled (due to a prior publication in Microprocessor Report believed by ISSCC to be too close.) 2) The RC6280 system was announced at 67.5MHz, in November 1989, with production shipments for 2Q90. It became clear that we weren't going to be able to ship many systems at that clock, and when we asked all our big customers if we should ship at 60MHz or wait until 67, not surprisingly, they all said "at 60MHz, it's the fastest micro that exists. Are you kidding? SHIP." Actually, this is an instructive sequence, not at all atypical: 1) ISSCC numbers are, by tradition "guaranteed never to exceed this", or, put another way "we got 1 chip to run at this speed in a tester". For instance, HP had a talk about a 90MHz chip (which is shipped in systems around 50-60? I think.) 2) When you put them in systems, there are all kinds of annoying intrusions from physical reality, like: 8ns SRAMs are not bought in the local store boards are not chips. systems are not boards. 3) When you are on the leading&bleeding edge, sometimes effective speeds and yields don't come up as fast as you expect. Even if you have a couple running in the lab @ X MHz, there's no guarantee that: you can manufacture a lot of them at X the next batch of chips, which have improvements that will make the sytem run at X+10%, will actually do so 4) An additional source of confusion is when different kinds of numbers get mixed up, like: ISSCC numbers, internal targets (for chips), internal targets (for systems), and margin adjustments (i.e., if the chips don't usually run, say 10% faster than what you ship, you may have no margin, and this is a no-no. 5) Will they ever run at 80MHz or more? Probably, but I certainly wouldn't hazard a guess as to when. So, like I said originally, this stuff is hard work, which can be seen by the number of ECL projects, described in public papers 6-9 months before we announced the RC6280, none of which have yet been shipped, and some of which (I think) have been cancelled or delayed. It's hard work, even with the huge amount of simulation that's done (of course, laeding-edge things always get to break the CAD tools, too :-) Again: a good lesson: even when you're close, even when you have them running in the lab, it's still hard to predict what you can manufacture, and when. Needless to say, it's even harder to accurately predict something that's not even in silicon yet, or not even designed. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086