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From: jfr@locus.com (Jon Rosen)
Newsgroups: comp.sys.mac.hardware
Subject: Re: LC Prediction (Was: New Macintosh Strategy)
Message-ID: <19271@oolong.la.locus.com>
Date: 8 Nov 90 17:57:55 GMT
References: <9037@ncar.ucar.edu> <9087@pitt.UUCP>
Distribution: na
Organization: Locus Computing Corp, Los Angeles
Lines: 29

In article <9087@pitt.UUCP> planting@cs.pitt.edu (Professor Harry Plantinga) writes:
>>Although the LC has a 68020 running at 16MHz (as does the Mac II), it is 
>>configured with a 16-bit data path to memory instead of the 32-bit data 
>>path of the Mac II. Since two bus cycles are required to read 32-bits  
>>from memory on the LC (where only one bus cycle is required on the Mac II),  
>>the LC is only half as fast as the Mac II, all other things being equal.
>
>16-bit data path, yes; half the speed, not necessarily.
>
>If I remember correctly, a data access on a Mac II has two wait states.  
>That means that a memory access takes 3 cycles.  If memory access on a Mac 
>LC has 2 wait states, it could be that the two transfers occur within 4 
>cycles.  That would make the LC 75% the speed of the II.
>
You have also overlooked the fact that the data path only effects memory
operations... Many instruction mix analyses that I have seen indicate
that only 25-35% of all instructions in a normal application load are
memory instructions (hence the effectiveness of RISC architectures)...
Most instructions are reg-to-reg arithmetic, bit twiddling, compares,
branches and the like... Since the 68020 is pipelined (8 byte pipe
I believe), its instruction queue will be filled most times to that
the smaller data path will not have that much effect on instruction 
fetches (they will be overlapped with other operations)... My guess
is that a 16-bit data path 020 would only see a 20-25% loss in speed
vs a 32-bit data path 020 given equal clock rates and no wait states.
If the above issue regarding wait states is also taken into account,
the difference might only be 15% slower...
 
Jon Rosen