Xref: utzoo comp.sys.mips:1156 comp.sys.dec:4429
Path: utzoo!attcan!uunet!cs.utexas.edu!wuarchive!mit-eddie!uw-beaver!uw-june!pardo
From: pardo@cs.washington.edu (David Keppel)
Newsgroups: comp.sys.mips,comp.sys.dec
Subject: DECstation cache configuration info wanted
Message-ID: <13644@june.cs.washington.edu>
Date: 6 Nov 90 19:41:50 GMT
Reply-To: pardo@june.cs.washington.edu (David Keppel)
Organization: University of Washington, Computer Science, Seattle
Lines: 16

I would like information about the cache configurations on various
MIPS-based DECstations: the size of the caches and the organization of
the caches (e.g., misses in the instruction cache are read from the
first-level data cache).

References to things in print is also useful.

Equivalent information for other MIPS-based products is of passing
interest to me.

Please e-mail, I will post a summary.  Thanks!

		;-D on  ( Cache and carry )  Pardo
-- 
		    pardo@cs.washington.edu
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