Xref: utzoo soc.culture.japan:5843 comp.sys.super:261 Path: utzoo!attcan!uunet!lll-winken!elroy.jpl.nasa.gov!ncar!noao!arizona!rick From: rick@cs.arizona.edu (Rick Schlichting) Newsgroups: soc.culture.japan,comp.sys.super Subject: Kahaner Report: Parallel Computing in Japan (Part 3) Message-ID: <120@saguaro.cs.arizona.edu> Date: 6 Nov 90 01:57:18 GMT Followup-To: soc.culture.japan Organization: U of Arizona CS Dept, Tucson Lines: 605 [Dr. David Kahaner is a numerical analyst visiting Japan for two-years under the auspices of the Office of Naval Research-Far East (ONRFE). The following is the professional opinion of David Kahaner and in no way has the blessing of the US Government or any agency of it. All information is dated and of limited life time. This disclaimer should be noted on ANY attribution.] [Copies of previous reports written by Kahaner can be obtained from host cs.arizona.edu using anonymous FTP.] To: Distribution From: David Kahaner ONRFE [kahaner@xroads.cc.u-tokyo.ac.jp] H.T. Kung CMU [ht.kung@cs.cmu.edu] Re: Aspects of Parallel Computing Research in Japan---Hitachi, Matsushita, and Japan Electronics Show 1990. Date: 6 Nov 1990 ABSTRACT. Some aspects of parallel computing research in Japan are analyzed, based on authors' visits to a number of Japanese universities and industrial laboratories in October 1990. This portion of the report deals with parallel computing at Hitachi and Matsushita, and some observations about the Japan Electronics Show 1990. PART 3. The following outline describes the topics that are discussed in the various parts of this report. PART 1 OUTLINE----------------------------------------------------------- INTRODUCTION SUMMARY RECOMMENDATIONS PART 2 OUTLINE----------------------------------------------------------- FUJITSU OVERVIEW Company profile and computer R&D activities VP2000 series supercomputer organization and performance PARALLEL PROCESSING ACTIVITIES SP (Logic Simulation Engine) AP1000 (Cellular Array Processor) RP (Routing Processor) ATM (Asynchronous Transfer Mode) Switch MISCELLANEOUS FUJITSU ACTIVITIES Neurocomputing HMET NEC SX-3 series supercomputer organization and performance Benchmark data for SX-3, VP2000, and Cray. Comments MISCELLANEOUS NEC PARALLEL PROCESSING ACTIVITIES PART 3 (this part) OUTLINE------------------------------------------------- HITACHI CENTRAL RESEARCH LABORATORY HDTV PARALLEL AND VECTOR PROCESSING Hyper crossbar parallel processor, H2P Parallel Inference Machine, PIM/C Josephson-Junctions Molecular Dynamics JAPAN ELECTRONICS SHOW, 1990 HDTV Flat Panel Displays MATSUSHITA ELECTRIC Company profile and computer R&D activities ADENA Parallel Processor MISCELLANEOUS ACTIVITIES HDTV Comments about Japanese industry PART 4 OUTLINE------------------------------------------------------------- KYUSHU UNIVERSITY Profile of Information Science Department Reconfigurable Parallel Processor Superscalar Processor FIFO Vector Processor Comments ELECTROTECHNICAL LABORATORY Sigma-1 Dataflow Computer and EM-4 Dataflow Comments CODA Multiprocessor NEW INFORMATION PROCESSING TECHNOLOGY Summary Comments UNIVERSITY OF TSUKUBA PAX SANYO ELECTRIC Company profile and computer R&D activities HDTV END OF OUTLINE------------------------------------------------------------ HITACHI CENTRAL RESEARCH LABORATORY. Kahaner has already written about Hitachi generally, and about some aspects of the CRL activities, see 21 Sept 1990 article "hitachi", so this report focuses only on those aspects of the visit that provided new insights. One important reason for our visit was for Kung to inquire about the possibility of using the CMU-Intel iWarp parallel processing system in HDTV applications. We had a meeting with Senior Chief Researcher Fukinuiki, (Telephone: (423) 23-1111, x 2009), who leads the technical part of Hitachi's HDTV program. Fukinuki is well known in the West and he showed us a paper from David Sarnoff Research Center in which his ideas were made the basis of a main part of their program. From the perspective of computation the needs are enormous. Requirements are for 10**5 to 10**10 integer operations per signal sample. At 28.6 MHz this requires at least (28.6*10**6)*(10**5)=2860 GigaOPS, and at 100 MHz at least 10 TeraOPS. Three dimensional processing will be even more demanding. Because of this high processing rate ASIC will be needed, in Fukinuiki's opinions. Programmable processors such as iWarp or DSP (digital signal processor) will be too slow and too expensive. Also, division is not needed, and all multiplications are by fixed constants (associated with filter coefficients) so special ROM for table lookup can be used. Hitachi is planning to build a special pipeline of ASIC blocks with 28.6 MBytes/sec or 100 MBtyes/sec bandwidth between connecting blocks. On the other hand, Fukinuki told us that he felt a fast general purpose parallel processor such as iWarp might be useful in those areas where real-time processing was not needed or processing rate needn't be that high, for example document preparation (e.g., image processing), robotics, or video phone (only requiring 64Kbit/second). Overall, this was a sobering meeting with a Japanese scientist who had clearly mastered his subject. HITACHI PARALLEL PROCESSING ACTIVITIES. We had very brief opportunities to visit three parallel processing projects. Below, we sketch the main ideas we were able to cull from our short visits. (1) Hyper crossbar parallel processor, H2P. This is a MIMD architecture with an unconventional interconnection network. The processors are first of all thought of as lying on a hypercube. The new ingredient is that all the processors on any plane parallel to a coordinate axis, i.e., on an cube face, are connected by a crossbar network. Thus only 2 "hops" are needed at most to connect any two processors. Hitachi is clearly trying to exploit their outstanding hardware capability in the design of the required crossbars and network routers. At the moment this is pure research, a paper computer. They have studied hyper crossbar structures that have the minimum number of switches for given numbers of processors. Hitachi is planning to build the crossbar and router chips within a year. H2P parallel systems of more than 1024 processors are envisioned. (2) Parallel Inference Machine, PIM/C. The "C" denotes their working language. This is a fairly conventional architecture, except for hardware support for typing. It is designed in the form of eight processors in a cluster, with one cluster fitting in a standard rack. The processors are on a bus using conventional snoopy caching. Currently there are two clusters built, and plans are that 32 clusters will be complete within a year. An interesting aspect of of the PIM/C architecture is that it has hardware support for load balancing. Another interesting point is that it uses a very impressive Hitachi mainframe pin array package, with 50 mil spacing. The contact is Dr. Mamoru Sugie Central Research Lab. Hitachi, Ltd. Higashi-Koigakubo, Kokubunji, Tokyo 185, Japan Tel: +81-423-23-1111 x3810 Email: sugie%crl.hitachi.co.jp (3) Josephson-Junctions. This work has been going on for about ten years, as part of the MITI HPP project, which ended this year. Activities involved not only Hitachi, but Fujitsu, and NEC too. Currently about 10 people are working on J-J. With the MITI project over Hitachi will certainly scale back their efforts, but will not terminate them. They have prototyped a 1 billion instruction per second superconducting microprocessor (with about 2K gates, in a 7mm by 7mm chip), and a 1KB RAM chip (also 7mm by 7mm). Currently switching time is about 10ps. Also they have discovered a new transistor design, which they believe that previous efforts, such as IBM's abandoned J-J effort, did not have. The researchers told us that practical application of this technology may be 10 to 20 years away. (4) Molecular Dynamics This is really an application of high speed computing needs. Dr. Shigeo Ihara in Hitachi's 7th Dept (ULSI Research Center) showed us his work on modeling the surface of Si(100). His research is rather different from conventional molecular dynamics models as it emphasizes the quantum mechanical model for computing the forces. Thus computing the forces is very expensive. His integration scheme is conventional, even somewhat old-fashioned, but the force calculation is the key time sink here. He claims that his model requires about 100 hours on an Hitachi S-810, which for this problem is about three times as fast as on a Cray 1. Even then he is only able to move around about 100 particles. His results indicate existence of interstitial dimer, not predicted before, recessed from the surface instead of vacancies as has been traditionally believed. However, he also acknowledged that the integration step size may still be too large and the results might be contaminated with numerical error. When we asked if it was possible to run this on a faster computer he explained that Hitachi would soon announce a faster supercomputer. JAPAN ELECTRONICS SHOW, 1990. We spent one free afternoon here and so were only able to get a general impression. This is surely one of the worlds largest such shows, with tens of thousands of square meters of exhibits in nine large buildings. Two hangar sized buildings were associated with consumer electronics, and all the rest were displays of very specialized parts and component technology. Not surprisingly, the consumer electronics buildings were mildly disappointing after seeing vast sections of Tokyo loaded with electronics stores. Also the exhibitors were not interested in displaying all their wares. This particular show was very clearly focused on HDTV, High Definition TeleVision, or HVTV (High Vision TV) as it is known here, with several hundred systems setup for display. So many different companies were exhibiting that we wondered why there was so much emphasis when there are almost no commercial systems available, videotapes, television broadcasts, and no likelihood of any for at least a few years. Serious broadcasting doesn't seem to be any closer than 1995, and some of the people we spoke to suggested that year 2000 was more likely for widespread household use. Further the price of current HDTV systems (to the extent that it can be estimated) is very high, and unless it can be knocked down by a factor of ten there will be little consumer interest. But, as all who have seen demonstrations will attest the systems are visually impressive and might even now be of interest in some specialized commercial situation where exceptional graphics will be important. We can also imagine that bars will buy HDTV for sports fans. MITI created a Hi-Vision Promotion Center (HVC) in 1988. This is a corporation whose members include all major HDTV manufacturers in Japan. According to their literature, "The Center promotes wider use of Hi-Vision technology in industry and by government organizations through identification, research, and analysis of problems existing in such public services as museums, medicine and education, and industrial areas (including theaters and amusements)." Currently, the government television network NHK is providing some HVTV time each week on an experimental basis, and some advertisements for commercial systems are beginning to appear in the papers. For HDTV to be of practical interest for transmission of live programs, or to store HDTV pictures on either laser disks or CD ROMs substantial research needs to be done. The main problem is that there is simply too much data. A typical HDTV picture contains about 1000 x 600 pixels in each of three colors, and frames come 30 times each second. Even with the best data compression algorithms now available a huge amount of data needs to be processed. This looks like a natural application for specialized parallel processing hardware and software, but to be practical the hardware must be inexpensive enough to be placed in every set. As we learned during our visits to Sanyo, Fujitsu, and Hitachi, there is active research going on in both real time data compression, and development of such specialized hardware. There is obviously a connection between success in this technology and success in other information processing activities. The Japanese companies are all more or less at the same point because they have been meeting in committees to establish standards, and this naturally leads to some sharing of information. Each company seems to have some very unique characteristics, although in a global sense they all seem to be pretty much alike. HDTV is another example of persistence in research; the U.S. gave up years ago, although there is still active research in Europe. The Japanese see the underlying technology here as a key one. As a specific example of the application of these ideas, the importance of ASIC, and the "last ten percent", we note that NEC has developed a hardware data compression system for color photographs using cosine transformations. The original color transmission system was developed earlier in Israel and U.K. but used software for the compression and decompression cycle. NEC has now built this using special purpose hardware. It is still much too slow for HDTV though. The Electronics show also gave us an opportunity to see not only many examples of HDTV, but also packaging, keyboards, liquid crystal projectors, and new flat panel displays. The Japanese have been performing research in flat panel technology for decades, initially for TV display, and well before there was even a glimmer about light, laptop computers. The flat panel screens have been adapted to TV use too, as can be attested to by Japan Air Lines first class passengers who get a three inch color set on a stalk attached to their armrest. As another example, Japan Broadcasting Corp. (NHK) has developed a 33inch plasma color display panel with a thickness of 6 mm weighing about 6kg. The flat displays also have obvious applications in vehicles, which merges very nicely with the growth of automobile navigation systems. MATSUSHITA ELECTRIC. This company is not well known in the west, even as their product names Panasonic, National, JVC, and Technics are. It is best known for its outstanding manufacturing capabilities (they even do manufacturing for IBM). Matsushita, founded in 1918, had sales last year of almost $40Billion U.S., and employs about 200,000. Sales, income, and net income have been growing at nearly 10 percent annually. The company's main growth areas are in communication and industrial equipment. Audio equipment, electronic components, semiconductors, batteries, and kitchen equipment have also grown but not quite as fast. They have identified six target areas for the future, information/communication, factory automation, semiconductors, autovisual, automotive electronics and housing/building products. This includes, specifically, HDTV, where they admit a huge investment will be needed to keep pace with the rapidly changing technology. As with many other large Japanese companies Matsushita hopes to become more global, and targets 1994 as the year when the ratio of internationally produced goods to total overseas business will be 50%. This year the first American President was appointed at Matshushita Electric Corp of America. In a similar way they hope to localize their R&D activities. One example is the Panasonic Advanced TV-Video Labs, in New Jersey. Also, as with other companies Matshushita really means many subsidiaries; in this case 117 companies in 38 countries. Corporate sales breakdown is as follows. Video equipment 27% Communication and industrial equipment 23 Audio equipment 9 Home appliances 13 Electronic components 13 Batteries & kitchen 5 Other 10 Kahaner reported on a visit to a National (Matsushita) factory, see 30 July 1990 file "flexible". The company was one of the first to incorporate fuzzy logic into their consumer products. Whatever one may think about the content of this technology, the public is enthusiastic about buying products described in this way. In addition to video cameras, Matsushita also markets fuzzy washing machines, vacuum cleaners, refrigerators, and air conditioners. The company owns a majority share in the Boulder, Colorado workstation maker, Solbourne Computer, and has begun to market the workstation. On our visit to Matsushita we asked why yet another Unix workstation, and were told that the company feels its performance is better than comparably priced Suns, and that it can be successful with this product if it is priced very competitively. Corporate R&D is divided into seven organizations and their suborganizations. We have annotated those labs that have major computer related research activities. Kansai Tokyo Information Equipment Research Laboratory Computer related activities include computer systems architecture, operating systems, compilers, natural language processing, machine translation, multimedia database systems, distributed parallel processing knowledge based and expert systems, development tools, image processing, communications systems such as optical, B-ISDN, satellite, networks, data storage equipment and printing equipment. Tokyo Information and Communications Development Center Audio Video Research Center Image Technology Research Laboratory Acoustic Research Laboratory Display Technology Research Laboratory Magnetic Recording Research Laboratory Materials and Devices Research Laboratory Computer related activities include HDTV research, and basic technology research in areas of video signal generation, processing, recording, display, transmission, compression, as well as display devices. High Definition Television Development Center Semiconductor Research Center VLSI Technology Research Laboratory VLSI Devices Research Laboratory Opto-Electronics Research Laboratory Living Systems Research Center Living Environmental Systems Research Laboratory Electrochemical Materials Research Laboratory Lighting Research Research Laboratory Central Research Laboratories Computer related activities in the area of intelligent mechanisms, human brain, natural systems, user friendly interfaces, multistage reasoning, fuzzy logic, neural networks, multimedia and hypermedia. Matsushita does not break out the number of employees engaged in research, but R&D expenditures (currently about $2.5Billion U.S.) are about 6% of sales and have been increasing at a higher rate. Confusingly, subsidiary companies have laboratories of their own. For example, Matsushita Electronics Corp has seven laboratories. Our visit was to the Central Research Labs in Osaka and focused on parallel computing and graphics applications. Frankly, we are not sure how these research projects fit into to list of topics above, as they seem more naturally associated with some other laboratories. Unlike many other Japanese companies which have prominent statues of their founders, Matsushita Central Research Laboratory has statues of great scientists from Japan and other countries, including Marconi, Ohm, and Edison in their courtyard. On the other hand, the dress code of everyone wearing overalls has only recently been removed, and we were also treated to the company marching song played like Muzak during our visit. Some of the Central Research Lab buildings (such as the Kadoma Building) are old and have an informal, cozy feeling, with an atmosphere like many American labs. This was the site of the oldest company lab and several of the buildings date back to before WWII. Our overall host for this visit was: Mr. Teiji Nishizawa, Manager Computer Architecture Kansai Information and Communications Research Laboratory Matsushita Electric Industrial Company Ltd. 1006 Kadoma, Kadoma-shi Osaka 571 Japan Tel: (06) 908-1291, Fax: (06) 903-0370 Email: NISHIZ@SY2.ISI.MEI.CO.JP ADENA (Alternating Direction Editing Nexus Array). ADENA was developed by Prof. Tatsuo Nogi Department of Applied Mathematics and Physics Kyoto University Yoshida Honmatchi, Sakyo-ku Kyoto 606 Japan Tel: (075) 753-7531 x5871, Fax: (075) 761-2437 Email: NOGI@KUAMP.KYOTO-U.AC.JP starting with work about ten years ago. The Matsushita group, while extremely knowledgeable about ADENA's hardware and system software, were less familiar with how it was to be used, and in fact we did not see ADENA operating while we were visiting Matsushita. Our hosts for this part of the Matsushita visit were Dr. Hirosha Kadota, Senior Staff Researcher Matsushita Electric Industrial Company Ltd. 3-15 Yagumo-Nakamachi, Moriguchi Osaka 570 Japan Tel: (06) 909-1121, Fax: (06) 906-3851. >From our visit it was not clear exactly what was Matsushita's basic interest in the machine; was it only to get their feet wet in the parallel processing area or to really develop and market a parallel computer for solving problems? However, Kahaner, has subsequently had an opportunity to see Nogi's laboratory in Kyoto and discuss ADENA with him in detail. Nogi claims that some Matsushita staff understand ADENA very well, as they are involved in not only the hardware but also the software development. Also, at least two of his former students are now working on the project at Matsushita. From those visits and examination of the technical papers the following summary is provided. At least three versions of a parallel processing computer called ADENA have been described by Nogi. The first was in 1980. Matsushita's version appears to be similar to what Nogi calls ADENA II. Basically it is a 256 node processor array that is attached to a host workstation. The current ADENAs are hosted by a Solbourne workstation via a VME bus. Sixteen processors fit on one board. The interconnection network is called a multi-layer crossbar, with maximum data transfer of 5.1Gbytes/second (each processor has about 20Mbytes/second input and output capability). This network shares one feature of the the hyper- crossbar network described above (Hitachi) in that communication between any two processors takes at most two hops, but in other ways is quite different. Nogi calls it a "skew" network and we describe it in some detail below. Each ADENA processor is a custom RISC. ADENA is organized to support numerical solution of partial differential equations using ADI (Alternating Direction Implicit) iteration schemes. Peak performance is 2.5GFLOP (per processor peak performance is 10MFLOP), but Nogi feels that about 1GFLOP is a more reasonable estimate. In fact, he has benchmarked "real" computational fluid dynamics applications at a few hundred MFLOPS. A special language ADETRAN, looking a great deal like Fortran extensions for other multiprocessors, has also been developed. Solving partial differential equations in three space dimensions and time has been one of the most important practical problems facing computational scientists, and is a ferociously active research area. Typically, integration is done at a discrete set of time points, with the computation at each time requiring the solution of a three dimensional potential equation, for which a prototype is Uxx+Uyy+Uzz = f(x,y,z) plus associated boundary conditions. The most common approach is to replace the differential equations with differences resulting in a large system of linear equations, whose solution u(i,j,k) on a mesh approximates U at the points (ih,jh,kh), where h is the mesh spacing. The matrix of the linear system is large and the equations are usually solved by iteration. In 1955 Peacemann and Rachford described one method to efficiently perform this iteration which they called ADI, an approach that is now known as "operator splitting". In simple ADI each iteration is composed of three sub-parts. First, one treats the Uyy+Uzz terms as known and solves the discretized equations associated with Uxx="known", then solves the Uyy="known", etc. (We are ignoring issues of acceleration to simplify the description.) This approach is potentially very efficient because at a fixed j and k solving for the numbers u(1,j,k), u(2,j,k),..., u(n,j,k) is easy; the system is tridiagonal. Furthermore, for different j and k the tridiagonal systems are independent and can be solved in parallel as long as all the data are available to each parallel solver. Solving Uyy="known" also requires the solution of a set of independent tridiagonal systems, etc. Thus in a parallel implementation each processor solves one tridiagonal system. The key point in any parallel implementation is that for efficient computation it is necessary for data computed in one processor to be quickly available to one or more of the others; thus between-processor data communication is a crucial aspect of parallel processing. The crossbar network is one solution to this problem; every processor is connected directly to every other, allowing data to be transferred between any two processors in one unit of time, or "hop". But large crossbars are expensive and difficult to build; the number of connections grows as the square of the number of processors. A thrust in much of today's parallel processing research is to design a compromise network, one that is not too costly but still efficient. For example, a two dimensional (torus) mesh network of k**2 processors has only about 2*k**2 connections, but communication between two processors can take as many as k hops. Of course, a good algorithm will not require data from far away processors and thus can be efficient on compromise networks. QCDPAX and AD1000 use torus networks. In the ADI example, processor (j,k) which solves the tridiagonal system for fixed j and k, only needs data from adjacent processors, those associated with j-1, j+1, k-1, and k+1. But when solving the next set of equations Uyy="known" the same processor appears to need data from a processor on the same row, but not adjacent. In the ADENA organization a set of data from processor (i,j) can be sent to (j,k). What this means is that when Uyy="known" is to be solved the user can visualize that the network of processors has "flipped" to allow only adjacent processors to be accessed. The actual network consists of 16 planes. On each plane, there are 16 busses of row direction and 16 busses of column direction. A 32 word FIFO queue is provided for each cross point of these busses. At the end of the busses Send/Receive Controller elements are provided which can send/receive group data to/from the addressed FIFO and automatically synchronize the operations. The most exciting thing about ADENA is that it is not a hypothetical machine; it is actually up and running. At Kyoto University, Kahaner watched the system in action. While he and Nogi were working, several other "real" users were also accessing the machine from elsewhere on the campus. Nogi claims that some physicists and engineers in different departments are doing useful work, primarily CFD. In fact, when Prof. C.T. Kelley, (North Carolina State University) visited the laboratory a month earlier he also noted that ADENA seemed to be in use and that "the computer appeared to be closer to a production model than a prototype." We also noted, as did Kelley, that the current bottleneck seems to be communication with the host via the VME bus. Nogi's users are writing programs in ADETRAN. We looked at some of these programs and they appeared perfectly straightforward, much more so than the description above would suggest. Nogi claims that the language is solid and that there is even a user's manual, unfortunately only in Japanese. He has already written several fundamental routines, not only ADI but FFT and some others. He also claimed that it was easy to break up problems that need more mesh cells than a 16 by 16 grid would provide, but we haven't looked at that issue in detail. An interesting thing about ADENA is about its possible commercial availability in the near future. So far three copies of the machine have been made. Matsushita recently made a product announcement, but while we were visiting the lab, we were told that it was a mistake and had been retracted. ADENA is the result of more than 10 years of research, and the originator has solid intuition for numerical techniques. We were told that the 256 processor (2.5 GFLOPS) ADENA will be sold for about $1Million U.S. It is not really possible to evaluate such a system without spending considerable time working with it on a day to day basis, but given its current state we feel that it would be very appropriate for a outside researcher to spend some time at Kyoto trying ADENA. Nogi explained that such researchers are welcome (in small numbers) but that he is very busy. A number of English language reports are available about ADENA. Two of the most recent and accessible are as follows. "Processing Element Design for a Parallel Computer", K Kaneko, M Nakajima, Y Nakakura, J Nishikawa, I Okabayashi, H Kadota, IEEE Micro, August 1990, pp26-38. "ADENA Computer III", T Nogi, Mem. Fac. Eng., Kyoto U, Vol 51, No. 2, 1989, pp135-152. MISCELLANEOUS MATSUSHITA ACTIVITIES. Matsushita is also hard at work on HDTV. They showed us one lab filled with HDTV related equipment. One experiment involves storing images on an optical disk (12" diameter) and studying how fast these can be brought up on the display. Currently they are able to store 600 images per disk, about 20 seconds worth of imaging. Recording and replay rates are 18Mbits/per second, much too slow for real time applications unless sophisticated image compression techniques are used. Video and audio are stored on the same disk, but at this point the key problems are still quantity of data, and transmission rates. We also looked some interesting parallel computers devoted to graphics. We saw photo-realistic image generation for office or home furnitures, and hardware and software systems to support real-time, interactive usages. The Matsushita graphics group has been doing everything, from hardware to software to application. This is typical of Japanese "don't give up any part of the technology" approach. At dinner we had an opportunity for some frank discussions about Japanese industrial practices, such as the status of women scientists, and the willingness of Japanese companies to hire Western researchers. Kung and Kahaner have both noticed the lack of women in research environments, and their almost total exclusion from more senior positions. This is related to Japanese custom, as many men still repeat the adage that "most women like to get married and stay home". Nevertheless, with a population predicted to peak in absolute terms early next century, women represent a critical resource in Japanese society. Both government and industry recognize this and have policies encouraging women, but we will have to wait to see if any real changes occur. Concerning Western researchers, it is also quite clear that Japanese industry is very happy to employ and sponsor these people, at least on a short term basis. When we asked, though, what chances a Westerner had, even one who was willing to make a long term commitment to a Japanese company, of working into a manager position, we were told "that would be very difficult". Perhaps things are better at Japanese subsidiaries in the west. ---------------END OF PART 3--------------------------------------------