Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!ut-emx!ccwf.cc.utexas.edu!tjk
From: tjk@ccwf.cc.utexas.edu (Todd Kelman)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Summary: The answer is in DMA...
Message-ID: <39251@ut-emx.uucp>
Date: 6 Nov 90 22:01:24 GMT
References: <1445.272CBD1B@ofa123.fidonet.org> <1990Oct31.194436.28242@idt.unit.no> <1990Nov5.063219.2266@research.canon.oz.au>
Sender: news@ut-emx.uucp
Reply-To: tjk@ccwf.cc.utexas.edu (Todd Kelman)
Organization: The University of Texas at Austin
Lines: 44

In article <1990Nov5.063219.2266@research.canon.oz.au> graeme@research.canon.oz.au (Graeme Wong See) writes:


>>In an old (autumn 1987) issue of BYTE they were testing 12 exTended memory 
>>expansion board. They measured and published figures for how much each board
>>slowed down the system, just by being installed... They even got different
>>figures for each board... They claimed that this slowdown was due to the extra
>>time it takes to refresh the extra RAM.
>>
>>I don't know much about this, but that's what the article said.. ( I read this
>>a week or so ago, so I'm sure about it..)
>>
>>	-Terje
>
>Quite possibly because the AT Bus is running at 8MHz, so refreshing that DRAM
>takes longer than refreshing DRAM on the motherboard which can be refreshed
>at a greater speed.
>
>graeme.
>-- 

The problem here stems from the fact that memory refreshing is usually
carried out through DMA cycles.  The implications of this are that the
microprocessor must give up the bus during a refresh cycle (a normal operation
of a DMA cycles, and thus cannot fetch or execute instructions that require
memory accesses (which is about all of them).  The exception is for cache
based systems, where the bus to the cache is seperate from the main memory
bus.  As long as there isn't a cache 'miss' then performace is not affected.
(There is more to it than that, however.  If the cache is implemented as 
a write-through, where all writes to the cache go through to main memory,
then you have the same problem.)

The conclusion is that for more memory, there will be more refresh necessary,
and thus more DMA cycles necessary, and more time where the processor must
release the bus to the memory controller.  I hope this clears things up.

By the way, please excuse the etiquette(lack thereof), since this is my
first attempt at a post.

-----------------------------------------
Todd Kelman (tjk@ccwf.cc.utexas.edu)
Computer Engineering and Computer Science
The University of Texas at Austin
-----------------------------------------