Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!uunet!motcid!koch
From: koch@motcid.UUCP (Clifton Koch)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Message-ID: <5093@navy22.UUCP>
Date: 7 Nov 90 15:28:18 GMT
References: <39251@ut-emx.uucp>
Organization: Motorola Inc., Cellular Infrastructure Div., Arlington Heights, IL
Lines: 41

->>>In an old (autumn 1987) issue of BYTE they were testing 12 exTended memory 
->>>expansion board. They measured and published figures for how much each board
->>>slowed down the system, just by being installed... They even got different
->>>figures for each board... They claimed that this slowdown was due to the extra
->>>time it takes to refresh the extra RAM.
->>>
->>Quite possibly because the AT Bus is running at 8MHz, so refreshing that DRAM
->>takes longer than refreshing DRAM on the motherboard which can be refreshed
->>at a greater speed.
->>
-> The problem here stems from the fact that memory refreshing is usually
-> carried out through DMA cycles.  The implications of this are that the
-> microprocessor must give up the bus during a refresh cycle (a normal operation
-> of a DMA cycles, and thus cannot fetch or execute instructions that require
-> memory accesses (which is about all of them).  The exception is for cache
-> based systems, where the bus to the cache is seperate from the main memory
-> bus.  As long as there isn't a cache 'miss' then performace is not affected.
-> (There is more to it than that, however.  If the cache is implemented as 
-> a write-through, where all writes to the cache go through to main memory,
-> then you have the same problem.)
-> 
-> The conclusion is that for more memory, there will be more refresh necessary,
-> and thus more DMA cycles necessary, and more time where the processor must
-> release the bus to the memory controller.  I hope this clears things up.

  It depends on how the refresh is implemented, on whether or not you'll
find a performance difference.  A DMA channel is used on PCs (unfortunately)
to refresh the DRAM.  Each chip has to have each row address read or written
every 4ms in order to refresh it.  The DMA controller refreshes by moving
a block of memory to itself.  If you have a single bank of DRAM (1 bank
being the number of chips necessary for one word width on the data bus)
then one block move will have to be done.  If
you expand the chips themselves, say from 1Mbyte to 4Mbyte chips, there
shouldn't be any impact on refresh.  If you expand memory by adding more
banks of DRAM, whether on the motherboard or on an aboveboard memory card,
the DMA controller has to hit more addresses so that each chip is refreshed,
and therefore has to do more block moves in the same 4ms.

  In a *real* refreshing scheme, you would refresh all banks at the same
time, or if you want to get tricky, stagger the bank refresh so that the
refresh of 1 bank coincides with a memory access to another bank.