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From: wilker@descartes.math.purdue.edu (Clarence Wilkerson)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Message-ID: <16325@mentor.cc.purdue.edu>
Date: 8 Nov 90 21:22:17 GMT
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Reply-To: wilker@descartes.math.purdue.edu (Clarence Wilkerson)
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This is a little hazy, but a few years back I rewrote the PAL on the
Zenith 150 memory board to use 256k chips. I seem to remember that there
was a special line to activate all banks during the refresh cycle.
I don't have the PAL equations handy to verify this right now.