Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!isc-br!jimc
From: jimc@isc-br.ISC-BR.COM (Jim Cathey)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Message-ID: <2964@isc-br.ISC-BR.COM>
Date: 9 Nov 90 01:48:17 GMT
References: <39251@ut-emx.uucp> <5093@navy22.UUCP>
Organization: ISC-Bunker Ramo, An Olivetti Company
Lines: 26

In article <5093@navy22.UUCP> koch@motcid.UUCP (Clifton Koch) writes:
>  It depends on how the refresh is implemented, on whether or not you'll
>find a performance difference.  A DMA channel is used on PCs (unfortunately)
>to refresh the DRAM.
>...
>If you expand memory by adding more
>banks of DRAM, whether on the motherboard or on an aboveboard memory card,
>the DMA controller has to hit more addresses so that each chip is refreshed,
>and therefore has to do more block moves in the same 4ms.

As I recall, PC memory boards are informed via the bus that a special
DMA on channel 0 is in progress, so they refresh all the rows of all
the chips at once rather than actually doing a DMA cycle.  Thus, the
PC's DMA only has to cycle 128 (or was it 256) times to refresh all the
memory regardless of the amount present.

It's _still_ a sucky way to do refresh.

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