Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!lll-winken!elroy.jpl.nasa.gov!sdd.hp.com!hplabs!otter.hpl.hp.com!otter!tgg
From: tgg@otter.hpl.hp.com (Tom Gardner)
Newsgroups: comp.arch
Subject: Re: chip cost
Message-ID: <780020@otter.hpl.hp.com>
Date: 9 Nov 90 09:03:42 GMT
References: <27547@mimsy.umd.edu>
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Lines: 17

|As I understand it (this information comes from my younger brother, who
|is doing device research at Penn State) you can shrink as much as you
|want.  The problem is that yeild goes to zero.

Not quite. Two interesting effects become apparent:
  - as the conductors become smaller and closer together the electrons
  tunnel from one conductor to a neighbouring one
  - as the transistors and conductors become smaller then, for a given
  current density (which is often a limiting factor), the current must
  reduce. Eventually you reach the point where, due to the quantised nature
  of current, there is a non-zero probability that there is no electron in
  the conductor/transistor, even though there is, on average, a current 
  flowing. 

About 8 years ago John Barker was indicating that these effects would begin
to become apparent as feature sizes shrink below 0.1um. Is there any more 
recent information?