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From: hamilton@dg-rtp.dg.com (Eric Hamilton)
Newsgroups: comp.arch
Subject: Re: The CPU with 3 brains
Message-ID: <1990Nov9.030627.22606@dg-rtp.dg.com>
Date: 9 Nov 90 03:06:27 GMT
References: <42737@mips.mips.COM> <2722@l.cc.purdue.edu> <7692.27393066@uwovax.uwo.ca>
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Reply-To: hamilton@dg-rtp.dg.com (Eric Hamilton)
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In article <7692.27393066@uwovax.uwo.ca>, brent@uwovax.uwo.ca (Brent
Sterner) writes:
|> In article <2722@l.cc.purdue.edu>, cik@l.cc.purdue.edu (Herman Rubin)
writes:
|> > In article <42737@mips.mips.COM>, mark@mips.COM (Mark G. Johnson)
writes:
|> > 
|> > 			....................
|> > 
|> > |        SPARC CPU:   30K gates   }     all of these reside on the
|> > |        MIPS CPU:    30K gates   }     same die, a 100K gate
array
|> > |        i286 CPU:    30K gates   }     in BiCMOS technology
|> 
|> 	Sorry if this has been suggested before, but why not:
|> 
|> 	   3 of	SPARC CPU:   30K gates		or
|> 	   3 of	MIPS CPU:    30K gates		or
|> 	   3 of	i286 CPU:    30K gates
|> 
|> 	ie, 3 different dies.  Integrate each with a symmetric
|> 	multi-processing os (ooops, my s/w background is showing :-)
|> 	to really exploit the capacity of the chip.  Most people I
|> 	know have a favourite system, and do *not* switch among
|> 	systems like the above (necessity excepted).  Could be a screamer
|> 	in a ws environment, provided you could handle the io.
|> --

Well, yeah, but how are you going to feed this beast?  It wants data
and instructions in vast quantities.....  Somehow you have to
deliver three instructions per clock cycle, and at least one
data transaction....

Put a unified cache in the chip with the three processors, and then
you'll have a system with no snooping/intervention/writeback
penalties.  That will run your favorite symmetrical multiprocessor
OS fast, if the cache is big enough.  But we're chewing up space at
a most discouraging rate.

You won't like the consequences of putting the cache outside.