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From: @crdgw1:raje@dolores.stanford.edu (exos:)
Newsgroups: comp.arch
Subject: chip cost
Message-ID: <2863@crdos1.crd.ge.COM>
Date: 9 Nov 90 01:35:56 GMT
Sender: davidsen@crdos1.crd.ge.COM
Lines: 83
To: exos:<@crdgw1:@dolores.stanford.edu:chris@mimsy.umd.edu>, davidsen


Hi,
This is wrt the chip yield articles in comp.arch. I think we might be
straying from comp.arch material so I decided to send you private mail.
If you feel this is appropriate for comp.arch, you are welcome to post it.

Your arguments are right in the most part, I just wanted to clarify a
few points.

>In article <27547@mimsy.umd.edu> chris@mimsy.umd.edu (Chris Torek) writes:
>   Anyway, assuming equipment and processing costs are equal for all sizes
>   (probably false, but...), all you have to do is maximize n_working_chips
>   in the following:
>
>	   area(chip) ~= devices(chip) * size(process)
>	   n_chips = area(die) / area(chip)
>	   P(dirt on chip) = total_dirt_on_die / area(chip)	[*]

Actually the probability that there will be "dirt on chip" is proportional
to the area of the chip, not inversely proportional. ie. a larger chip is
more likely to have a defect. Actually the distribution is not quite so
straightforward, and using Binomial statistics the simplistic yield equation
is     

  yield = fraction of working chips in a wafer =  e^(- lambda Chiparea)
                                                     .......(1)
 where lambda = Average defects per unit area of the wafer
 
lambda is a function of the technology - ie lambda is larger for more
agressive technologies and also of the "maturity" of the technology - ie IC
fabs strive to reduce lambda on the same process by "getting better at
manufacturing the technology".

Now the total number of working chips is

  Working chips = Total Chips in the wafer * yield

                = N e^(-lambda Waferarea/N)           .......(2)

This is of course a continuously increasing function of N for constant lambda.
So for any given technology you could get more and more working chips
from a wafer but they would hold fewer and fewer devices and of course this
would be pointless to pursue too far.

By scaling devices down, the same function can be accomplished
in a smaller Chiparea but lambda increases and the yield (Eqn 1)
may initially go down.

There are two factors that mitigate the loss of yield in a more agressive 
technology
1. lambda eventually reduces as one progresses along the learning curve
2. The number of chips (N) in the wafer is larger because of the smaller
Chiparea and hence the total number of Working chips (Eqn 2) could be
made larger even if the lambda stays at a higher value than before.

And of course keep in mind that these chips will be faster and consume
lesser power.

Current predictions are that device scaling will pretty much stop at the
0.25um MOSFET gate length level. The problems are 
1. reliability of devices
 - hot electron effects
 - breakdown of oxides
 - punchthrough
 - unstable threshold voltages
 - statistical behaviour - 0.25umx0.25um MOSFET with an 80A oxide at 2V 
 gate bias has just around 3000 electrons in the channel!),
 
2. reliability of interconnects 
 - worsens as the fifth power of device scaling
 - electromigratoin
 - contact resistance
 - interconnect delay dominating total delay of device

3. Manufacturing issues
 - lithography limits (could be solved by e-beam)
 - etching limits (aspect ratios in DRAMS are as high as 10)

4. Design issues, testing, and a whole host of others ..

But the march continues, relentless.

Prasad