Xref: utzoo comp.arch:19148 rec.arts.sf-lovers:49366 alt.cyberpunk:4950
Path: utzoo!utgpu!cs.utexas.edu!uunet!mcsun!ukc!tcdcs!dce.ie!jp
From: jp@dce.ie (John Pelan)
Newsgroups: comp.arch,rec.arts.sf-lovers,alt.cyberpunk
Subject: Re: Count Zero Interrupt
Keywords: interrupt, zero, counter
Message-ID: <1990Nov10.002854.14069@dce.ie>
Date: 10 Nov 90 00:28:54 GMT
References: <1427@carol.fwi.uva.nl> <4bC2VW600VIE094FUA@andrew.cmu.edu> <9438@fy.sei.cmu.edu>
Organization: Datacode Communications Ltd, Dublin, Ireland
Lines: 21

The exact quote is;

COUNT ZERO INTERRUPT
-On receiving an interrupt, decrement the counter to zero.

Note that this is neither when a counter underflows generate an interrupt
or when an interrupt is generated 'reset' the counter to zero.

The term looks decidedly made-up and has no resemblance to any m/c instruction
or counter chip function that I've ever encountered. For it to be m/c the
CPU must have some sort of counter (*not* the same as a register!). It'd
definitely have it's uses (for pulse generation say) but not enough that
it'd warrant an instruction all of its own. You could quite easy implement it
with a couple of instructions on any CPU. Looks like Gibson was misinformed
or he misquoted.

-- 
John Pelan  (jp@dce.ie)
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Splice the main() brace { | Traditional nautical programmers saying.
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