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From: msp33327@uxa.cso.uiuc.edu (Michael S. Pereckas)
Newsgroups: comp.arch
Subject: Re: superconcurrency and the cpu with 3 brains
Keywords: superconcurrency shared-memory
Message-ID: <1990Nov10.211535.1087@ux1.cso.uiuc.edu>
Date: 10 Nov 90 21:15:35 GMT
References: <1990Nov8.211217.4165@ux1.cso.uiuc.edu> <1990Nov9.213205.8026@idayton.field.intel.com>
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Organization: University of Illinois at Urbana
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In <1990Nov9.213205.8026@idayton.field.intel.com> jimf@idayton.field.intel.com (Jim Fister) writes:


>Something like the i860?  

>Sorry, couldn't resist.  Anyway, I've heard talk of people counting all of 
>the transistors in, say, a Cray and thinking something like, gee, my micro
>budget in the year 2000 will be twice that big.  What's to say that some
>company won't just sweep some parallel supercomputer onto sand in the not-so-
>far future?  AMD and Intel both have onsey, twosey pc-on-a-chip parts now.
>Somebody should be putting a real computer (define real: non-DOS) there
>any day, right?

I don't claim to have any expertise in this (or much of anything
else), but doesn't putting the cpu on a large number of chips instead
of just one help with the I/O pin problem?  If you put a Y/MP cpu on
one chip, how many pins would you need?  And don't forget power and
ground pins.  The Cray-3 and the latest NEC design are interconnect
nightmares as it is.  

The i860 is bottlenecked at the memory bus.  (so was the Cray-1).
Multiple memory ports and a memory divided into many banks (like the
X/MP / /Y/MP) can greatly increase performance.  If you want to read 2
and write 1 word with each clock, you are going to need a lot of
wires, and you need to do that to operate on long vectors at ~1
FLOP/CLOCK.  The i860 reaches its peak only when one operand is a
constant.

--
Michael Pereckas               * InterNet: m-pereckas@uiuc.edu *
just another student...          (CI$: 72311,3246)
*Jargon Dept.: Decoupled Architecture--sounds like the aftermath of a tornado*