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From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: 1 double or 2 singles
Message-ID: <11054@pt.cs.cmu.edu>
Date: 11 Nov 90 21:50:22 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 15


Various defunct (ETA, Cydrome) and extant (Cray) machines have a
trick, whereby a floating point pipe can deliver one double precision
result per clock, or else deliver two single precision results per
clock.

This always sounded vaguely reasonable, at least at the pin-count
level, but I've never read an analysis of the circuit issues.

I can't think of a single micro offering this feature. I understand
why it's not in the unpipelined FPUs, and I understand why it's not
in the FPUs that emphasize 32-bit data paths. But why isn't it in any
micro? Is the idea dead for good, or about to come back?
-- 
Don		D.C.Lindsay