Path: utzoo!attcan!uunet!mcsun!hp4nl!charon!dik
From: dik@cwi.nl (Dik T. Winter)
Newsgroups: comp.arch
Subject: Re: 1 double or 2 singles
Message-ID: <2511@charon.cwi.nl>
Date: 11 Nov 90 22:40:35 GMT
References: <11054@pt.cs.cmu.edu>
Sender: news@cwi.nl
Organization: CWI, Amsterdam
Lines: 22

In article <11054@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
 > 
 > Various defunct (ETA, Cydrome) and extant (Cray) machines have a
What Cray are you refering to?
 > trick, whereby a floating point pipe can deliver one double precision
 > result per clock, or else deliver two single precision results per
 > clock.

 > I can't think of a single micro offering this feature. I understand
 > why it's not in the unpipelined FPUs, and I understand why it's not
 > in the FPUs that emphasize 32-bit data paths. But why isn't it in any
 > micro? Is the idea dead for good, or about to come back?
Offhand I would say that the idea requires a doubling of all hardware to
do the arithmetic.  This appeared to be feasable in the 205/ETA, the
machine costs enough, and the wires for the 64 bit wide datapath (and
128 bits wide internally) were there anyway.  Another thing to note is
that the 205/ETA offers this facility in the vector instructions (those
are memory to memory) but not in the scalar instructions (those are
register to register).
--
dik t. winter, cwi, amsterdam, nederland
dik@cwi.nl