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From: spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves)
Newsgroups: comp.arch
Subject: registerless architecture
Message-ID: <1990Nov12.145410.29035@cs.cmu.edu>
Date: 12 Nov 90 14:54:10 GMT
Sender: netnews@cs.cmu.edu (USENET News Group Software)
Reply-To: spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves)
Organization: Carnegie Mellon University
Lines: 30


Has anyone every thought about or done a registerless architecture?
registers, after all, are just a sort of cache, another level in the
memory hierarchy.  but a fixed size, hard-wired one.  Consider
a machine with a 4 level memory

0) the fpu and alu      0Kb
1) on-chip cache       10Kb
2) normal cache       100Kb
3) main ram        10 000Kb
4) magnetic disk  100 000Kb

It is very easy expand the size/speed of caches, but not to add registers.
I think this is a big advantage.  The way a cache works generalizes
the behavior things like register windows.

One problem is that instructions would have to be very large (3 addresses).
using a stack based approach would help.  The 3 addresses are then
relative to the stack pointer, and can be small enough to fit into the
instruction. That's 8 or 9 bits for 32 bit machines, or twice that
for 64 bit machines.  again, it scales easily.

context switch is fast and easy, there's nothing but CCR, PC, and FP.

any thoughts on this?  stupid idea, or the wave of the future?  :)


			Consume
Scott Draves		Be Silent
spot@cs.cmu.edu		Die