Path: utzoo!attcan!uunet!brunix!cgy
From: cgy@cs.brown.edu (Curtis Yarvin)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Keywords: cache
Message-ID: <56084@brunix.UUCP>
Date: 12 Nov 90 15:48:32 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu>
Sender: news@brunix.UUCP
Reply-To: cgy@cs.brown.edu (Curtis Yarvin)
Organization: Brown University Department of Computer Science
Lines: 31

In article <1990Nov12.145410.29035@cs.cmu.edu> spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) writes:
>
>Has anyone every thought about or done a registerless architecture?
>registers, after all, are just a sort of cache, another level in the
>memory hierarchy.  but a fixed size, hard-wired one.

>One problem is that instructions would have to be very large (3 addresses).
>using a stack based approach would help.  The 3 addresses are then
>relative to the stack pointer, and can be small enough to fit into the
>instruction. That's 8 or 9 bits for 32 bit machines, or twice that
>for 64 bit machines.  again, it scales easily.

This is one of the only two reasons to use registers.  The other is that
registers can still be made a bit faster; no association or anything necessary
(this goes unless you are one of those direct-mapped cache people).  This
capability isn't much used in practice, though - generally both register
and cache hits take one clock cycle.

>context switch is fast and easy, there's nothing but CCR, PC, and FP.

Ah, but no... you have to flush your cache anyway, you don't really
gain anything here.

>Scott Draves		Be Silent
>spot@cs.cmu.edu		Die

		-Curtis

"I tried living in the real world
 Instead of a shell
 But I was bored before I even began." - The Smiths