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From: msp33327@uxa.cso.uiuc.edu (Michael S. Pereckas)
Newsgroups: comp.arch
Subject: Re: 1 double or 2 singles
Message-ID: <1990Nov12.160009.28675@ux1.cso.uiuc.edu>
Date: 12 Nov 90 16:00:09 GMT
References: <11054@pt.cs.cmu.edu> <2511@charon.cwi.nl> <11056@pt.cs.cmu.edu>
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I don't know how hard it would be to do, but I wonder how useful it
would be.  Does anyone know how useful it was on the Cyber 205?  

I wonder how you would keep such a unit busy on a micro.  Keeping a
fully pipelined version busy would require 1 instruction, 128 bits of
data, and a place to put 64 bits of results per cycle.  This would be
easier as a vector instruction in a vector machine (as in the CDC
machines).  

A non-fully pipelined version would be easier to feed, and might have
advantages over a more-fully pipelined conventional single-precision
unit, in that you could do the same work with half the floating-point
instructions.  If instruction issue is a bottleneck, than this could
help, but there are probably easier ways.  (How about a set of fp
instructions that code for two successive fp operations.  Then you get
the same thing, and complicate control and issue instead of the fp
functional units.  This may or may not be better.) 


--
Michael Pereckas               * InterNet: m-pereckas@uiuc.edu *
just another student...          (CI$: 72311,3246)
*Jargon Dept.: Decoupled Architecture--sounds like the aftermath of a tornado*