Path: utzoo!attcan!uunet!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!uflorida!travis!tom From: tom@ssd.csd.harris.com (Tom Horsley) Newsgroups: comp.arch Subject: Re: registerless architecture Message-ID: Date: 12 Nov 90 17:28:00 GMT References: <1990Nov12.145410.29035@cs.cmu.edu> Sender: news@travis.csd.harris.com Organization: Harris Computer Systems Division Lines: 32 In-reply-to: spot@WOOZLE.GRAPHICS.CS.CMU.EDU's message of 12 Nov 90 14:54:10 GMT >>>>> Regarding registerless architecture; spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) adds: spot> Has anyone every thought about or done a registerless architecture? spot> registers, after all, are just a sort of cache, another level in the spot> memory hierarchy. but a fixed size, hard-wired one. Consider spot> a machine with a 4 level memory Once a long long time ago in a universe far far away I worked on a compiler for a new machine that was going to be registerless because, as the engineers said, "cache is just as fast as registers anyway". By the time we got to the point where they were ready to cancel the project the engineers had taken to pleading with the compiler writers to come up with some way to allocate variables in locations such that frequently used variables would be in spots that didn't get cache collisions with other frequently used variables... There is a common technique for doing something like this in compilers. It is called "register allocation". Unfortunately, it is orders of magnitude more difficult to do when there are no registers... spot> any thoughts on this? stupid idea, or the wave of the future? :) Stupid idea (that's your phrase, not mine :-). -- ====================================================================== domain: tahorsley@csd.harris.com USMail: Tom Horsley uucp: ...!uunet!hcx1!tahorsley 511 Kingbird Circle Delray Beach, FL 33444 +==== Censorship is the only form of Obscenity ======================+ | (Wait, I forgot government tobacco subsidies...) | +====================================================================+