Path: utzoo!attcan!uunet!ns-mx!pyrite.cs.uiowa.edu
From: jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Message-ID: <3168@ns-mx.uiowa.edu>
Date: 12 Nov 90 18:02:50 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu>
Sender: news@ns-mx.uiowa.edu
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From article <1990Nov12.145410.29035@cs.cmu.edu>,
by spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves):
> 
> Has anyone every thought about or done a registerless architecture?

My Ultimate RISK (Computer Architecture News, 1988) is a memory-to-memory
architecture with no registers in the instruction execution unit other
than the PC.  It has no arithmetic unit in the IEU either, which is why
I call it an IEU instead of a CPU.  The registers and arithmetic unit(s)
are out on the memory bus.  It was proposed as a purely pedagogical
exercise, but it can be pipelined to death, and with appropriate ALU(s)
out on the bus, it can be quite powerful.  I gather a few people have
built or are building machines based on my design, but I haven't heard
much from them.
					Doug Jones
					jones@herky.cs.uiowa.edu