Path: utzoo!attcan!uunet!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: registerless architecture Message-ID: <43085@mips.mips.COM> Date: 12 Nov 90 19:06:23 GMT References: <1990Nov12.145410.29035@cs.cmu.edu> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 34 In article <1990Nov12.145410.29035@cs.cmu.edu> spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) writes: >Has anyone every thought about or done a registerless architecture? >registers, after all, are just a sort of cache, another level in the >memory hierarchy. but a fixed size, hard-wired one. Consider .... >It is very easy expand the size/speed of caches, but not to add registers. >I think this is a big advantage. The way a cache works generalizes >the behavior things like register windows. .... >using a stack based approach would help. The 3 addresses are then >relative to the stack pointer, and can be small enough to fit into the >instruction. That's 8 or 9 bits for 32 bit machines, or twice that >for 64 bit machines. again, it scales easily. Bell Labs' CRISP chips were this way. This architecture was a fairly elegant evolution of the register windows path, i.e., it had a true "stack cache", with on-chip registers laid fairly invisibly over the top of the stack. I.e., register numbers were really offsets from the stack pointer, and if they were within range, you got the register, else had to fetch the data. Of interest to compiler writers was the fact that if you generated an address via other routes, and the address was in the stack cache, you got it also, eliminating the need to deal with address aliasing (i.e., x ... y = &x; func(y)). So, anyway, they've been built, and serious software work done with them, although CRISPs never did get to the commercial market, which is a little sad. (I may disagree with some of the design choices, but it did have some elegant ideas.) -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086