Path: utzoo!attcan!uunet!munnari.oz.au!sirius.ucs.adelaide.edu.au!sirius!jeremy From: jeremy@cs.adelaide.edu.au (Jeremy Webber) Newsgroups: comp.arch Subject: Re: registerless architecture Message-ID: Date: 12 Nov 90 23:29:18 GMT References: <1990Nov12.145410.29035@cs.cmu.edu> Sender: news@ucs.adelaide.edu.au Organization: Digital Arts Film and Television Lines: 21 Nntp-Posting-Host: chook.ua.oz.au In-reply-to: spot@WOOZLE.GRAPHICS.CS.CMU.EDU's message of 12 Nov 90 14:54:10 GMT In article <1990Nov12.145410.29035@cs.cmu.edu> spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) writes: Has anyone every thought about or done a registerless architecture? Have a look at the INMOS Transputer. It has 3 general purpose registers, which aren't addressed directly, but via stack operations. It also has a small amount of on-chip 1-cycle RAM, mapped into the processor's address space. Its negatives are no memory management support, and the on-chip RAM isn't a cache, it is hardwired into the low memory addresses. Still, they have a lot of virtues, particularly if you're rolling your own hardware. -jeremy -- -- Jeremy Webber ACSnet: jeremy@chook.ua.oz Digital Arts Film and Television, Internet: jeremy@chook.ua.oz.au 3 Milner St, Hindmarsh, SA 5007, Voicenet: +61 8 346 4534 Australia Papernet: +61 8 346 4537 (FAX)