Path: utzoo!attcan!uunet!bu.edu!purdue!mentor.cc.purdue.edu!l.cc.purdue.edu!cik
From: cik@l.cc.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Message-ID: <2731@l.cc.purdue.edu>
Date: 13 Nov 90 00:53:18 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu>
Organization: Purdue University Statistics Department
Lines: 45

In article <1990Nov12.145410.29035@cs.cmu.edu>, spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) writes:
 
> Has anyone every thought about or done a registerless architecture?
> registers, after all, are just a sort of cache, another level in the
> memory hierarchy.  but a fixed size, hard-wired one.  Consider
> a machine with a 4 level memory
 
> 0) the fpu and alu      0Kb
> 1) on-chip cache       10Kb
> 2) normal cache       100Kb
> 3) main ram        10 000Kb
> 4) magnetic disk  100 000Kb
 
> It is very easy expand the size/speed of caches, but not to add registers.
> I think this is a big advantage.  The way a cache works generalizes
> the behavior things like register windows.
 
> One problem is that instructions would have to be very large (3 addresses).
> using a stack based approach would help.  The 3 addresses are then
> relative to the stack pointer, and can be small enough to fit into the
> instruction. That's 8 or 9 bits for 32 bit machines, or twice that
> for 64 bit machines.  again, it scales easily.
 
> context switch is fast and easy, there's nothing but CCR, PC, and FP.
 
> any thoughts on this?  stupid idea, or the wave of the future?  :)

Even with registers, it is sometimes necessary to change code, but it can
be  made infrequent.  Without registers, ugh!

Only a 9-bit field relative to a pointer?  One of the stupid (in my opinion)
things about the 86-class machines is the 16 bit field relative to a pointer,
and more than one such field could be active.  

Indirect addressing and addressing relative to registers is extremely 
important; to replace registers with cache intelligently would require
allowing arbitrary depth of indirection, which is not a bad idea.  But
there would be at least a cache access for each one.  Also, the idea of
allowing instructions of arbitrary address length seems to be out of
fashion.  It would allow indexing of registers, which should be allowed
anyhow.
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)