Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!apple!voder!dtg.nsc.com!my
From: my@dtg.nsc.com (Michael Yip)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Keywords: Transputer, Register
Message-ID: <1510@frapper.nsc.com>
Date: 12 Nov 90 18:48:38 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu>
Reply-To: my@frapper.UUCP (Michael Yip)
Distribution: usa, na
Organization: National Semiconductor, Santa Clara
Lines: 32

Someoen mentioned about a registerless architecture but using 
large on chip cache instead of the registers.  The reason was
registers limit the machine architecture and instruction sets
and expanding the cache is easier than adding more registers.

The transputers (eg T400, T800) are basically "registerless"
machines.  Transputer is basically a "stack based RISC machine"
which does not use any registers other than the 3 temporary
stack registers.  Instructions operate on the stack instead 
of registers.  The Transputers have on chip RAM (not cache) for
storage, therefore the context of a process including the 
content of the stack can be stored on the on chip RAM.  I think
that newer transputers also use caches, but I am not sure 
anymore since I only designed with the transputer a long time
ago when it first came out.  

So does the Transputer architecture fit into the registerless
computer architecture?

By the way, I think that the AT&T Crisp (????) is also a 
stack base machine.  But I don't know any detail about it.

About instructions and the number of registers ... doesn't
the register windowing technique also solve the problem since
the instruction set does not really depend on the number of 
total registers available on the chip (but the number of 
registers available at one time.)

Just my $0.02!  ;)

-- Mike
   my@dtg.nsc.com