Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!agate!shelby!neon!pescadero.Stanford.EDU!philip
From: philip@pescadero.Stanford.EDU (Philip Machanick)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Message-ID: <1990Nov13.182307.19709@Neon.Stanford.EDU>
Date: 13 Nov 90 18:23:07 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu> <1990Nov13.035859.4777@relay.wpd.sgi.com>
Sender: news@Neon.Stanford.EDU (USENET News System)
Reply-To: philip@pescadero.stanford.edu
Organization: Computer Science Department, Stanford University
Lines: 33

In article <1990Nov13.035859.4777@relay.wpd.sgi.com>, bean@putter.wpd.sgi.com (David (Bean) Anderson) writes:
|> In article <1990Nov12.145410.29035@cs.cmu.edu>, spot@WOOZLE.GRAPHICS.CS.CMU.EDU (Scott Draves) writes:
|> |> 
|> |> Has anyone every thought about or done a registerless architecture?
[detail deleted]
|> |> One problem is that instructions would have to be very large (3 addresses).
|> |> using a stack based approach would help.  The 3 addresses are then
|> |> relative to the stack pointer, and can be small enough to fit into the
|> |> instruction. That's 8 or 9 bits for 32 bit machines, or twice that
|> |> for 64 bit machines.  again, it scales easily. [stuff deleted]
|> |> any thoughts on this?  stupid idea, or the wave of the future?  :)
[more deleted]
|> 2.  Why are registers considered a *problem*?   Modern compilers usually
|> do a good job of effectively using the registers as opposed to *stupid*
|> cache hardware.  Indeed, some interesting work in "blocking algorithms"
|> (faking the cache into behaving like a large register file) have resulted
|> in some impress performance figures.
|> 
|> 3.  The HP3000 is a stack machine with no GPRs.  The hardware (on
|> some models) would keep the top four stack items in a register file
|> in order to increase performance.  
[more deleted]

In fact, I believe the Burroughs B5500 series introduced this registers at top
of stack scheme. This was a very pure stack-based architecture, with most
instructions relative to top of stack. Because they had no addresses, they
were packed 4 to a 48-bit word. Very efficient? See Hennessy and Patterson
"Computer Architecture: A Quantitative Approach", Morgan Kuffman, 1990 for
why RISC performs better. In other words, this is not a stupid idea, just
one that's been tried and not delivered - a wave of the past, if you will.
-- 
Philip Machanick
philip@pescadero.stanford.edu