Path: utzoo!attcan!uunet!cs.utexas.edu!sdd.hp.com!usc!ucsd!ucbvax!bloom-beacon!eru!hagbard!sunic!isgate!krafla!adamd From: adamd@rhi.hi.is (Adam David) Newsgroups: comp.os.cpm Subject: Re: Does Zilog have a *** 20MHz *** Z80? Message-ID: <2402@krafla.rhi.hi.is> Date: 11 Nov 90 18:38:37 GMT References: <1990Nov1.174451.28750@techbook.com> <2288@bnlux0.bnl.gov> <1315@bilver.UUCP> Organization: University of Iceland Lines: 38 In <1315@bilver.UUCP> bill@bilver.UUCP (Bill Vermillion) writes: >In article <2288@bnlux0.bnl.gov> scott@solids.phy.bnl.gov (david scott coburn) writes: >>In article <1990Nov1.174451.28750@techbook.com> fzsitvay@techbook.com (Frank Zsitvay) writes: >>>what i really want is a 12 to 16 mhz z80 code compatible processor. >>>does anyone know if such a beast exists?? The Zilog Z180 is available to 10MHz, Maybe a 12MHz 64180 can be had from Hitachi (?). I've seen the info booklet on 20MHz Z80 from Zilog. It looks like a nice piece of work. Don't know anything about delivery times yet, but it ought to be available by now. >I have a Xenix system I take care of that uses a Z280 at 20MHz to >handle up to 32 serial ports. Isn't the Z280 upward compatible. The crystal oscillator is run at 20MHz but this is divided by two to give 10MHz to the actual works. In preliminary product specs a 16MHz version was mentioned, which would be clockable at 32MHz. In later literature only the 10 MHz version remains. Actual execution is faster on a Z280 than a standard Z80 at similar speeds because of pipelining and caching. There is also an option to use a 16-bit data bus. The Z280 in system mode can be (very almost) 100% code compatible with the Z80. Any code that relies on the R register being incremented every opcode fetch will not work, because all 8 bits of what is stored there with LD R,A remains unchanged until the next LD R,A or system reset. There is a whole wealth of new instructions and addressing modes, some of which are more useful than others. The Z80-bus (8-bit) hardware interface is slightly less than actually compatible. The main difference is that M1L signal is output only during IM0 interrupt acknowledge or RETI instruction fetch. (no other fetches). The refresh rate can be programmed but there will not be a refresh at the end of each opcode fetch, as with the Z80. Also the lower 8 bits of the address bus need to be demultiplexed from the data bus. Single-stepping and other hardware traps are supported. A third interrupt mode provides more flexibility. Most of the time these differences won't actually matter, and should even make design easier. Adam David. adamd@rhi.hi.is