Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cmcl2!yale!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!usc!apple!uokmax!slfields From: slfields@uokmax.ecn.uoknor.edu (Scott L Fields) Newsgroups: comp.sys.amiga.hardware Subject: Re: RISC Amiga WHat's RISC? Message-ID: <1990Nov14.015849.4692@uokmax.ecn.uoknor.edu> Date: 14 Nov 90 01:58:49 GMT References: <1990Nov9.222501.21238@engin.umich.edu> Distribution: usa Organization: Engineering Computer Network, University of Oklahoma, Norman, OK Lines: 28 In article Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips) writes: >>>>>> On 9 Nov 90 22:25:01 GMT, milamber@caen.engin.umich.edu (Daryl Scott Cantrell) said: >Daryl> RISC == Reduced Instruction Set Computing. >Daryl> I've seen 1.2-1.3 cyc/ins all over the place.. > >Ditto for the 80486. (No flames, please:-) However, there are current >RISC processors that manage to average _less_ than 1 cycle per instruction. >(I've even heard of 1/2-1/3 Cycles Per Instruction peak performance. How >_do_ they do that?) That is not an easy question to answer. If you pipeline the incoming instruct- ion stream, then the instructions are simply queued up. On the other hand, if you have more than one instruction sequencer, you can start running those instructions. The problem is that you have to keep on eye out for instructions that would modify the following instructions. example-> if the first instruct- ion in the queue is add r1 to r2, then you don't won't the next instruction modifying the values in r1 or r2 until the first instruction completes. God, that is a simplified approach but should get the idea across. I would see problems if you ever got a uniform 1 cycle/instruction CPU though. If every cycle you fetch a new instruction, how can you prefetch the next instruction into the queue? I am not into RISC design so, at the moment, such solutions escape me. I do know that the IBM 860 {maybe the 960} CPU averages about 3 instructions a cycle. You could achieve the same types of number for CISC chips with this kind of architecture but you would need to design programs with this in mind. Imagine a 68050 with a average cycle time of 4 instructions at 50 Mhz. Then again, think of the number of transistors to make the BEAST! Any further discussion merited? Please, speak your peace.