Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!elroy.jpl.nasa.gov!turnkey!orchard.la.locus.com!fafnir.la.locus.com!fafnir.la.locus.com!dlt From: dlt@locus.com (Dan Taylor) Newsgroups: comp.sys.amiga.hardware Subject: Re: RISC Amiga WHat's RISC? Message-ID: Date: 15 Nov 90 00:34:05 GMT References: <39367@ut-emx.uucp> <15759@cbmvax.commodore.com> <1990Nov9.222501.21238@engin.umich.edu> Organization: Locus Computing Corporation, Los Angeles, California Lines: 45 Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips) writes: >>>>>> On 9 Nov 90 22:25:01 GMT, milamber@caen.engin.umich.edu (Daryl Scott Cantrell) said: >Daryl> RISC == Reduced Instruction Set Computing. >Just a few months ago, I thought that also. (I was then a RISC basher, >BTW.) As it turns out, RISC is a misnomer. The cornerstone of RISC is >ruthless _quantitative_ analysis; features (instructions, cache, etc.) are >only added as they prove themselves _quantitatively_ (cost/performance) >when executing _real programs_. >Daryl> Of course, RISC will never really be that much faster than CISC >Daryl> because CISC chips can always bail out.. By pipelining their >Daryl> architecture for the "most-used" instructions that RISC chips >Daryl> implement, and still having the higher-level functions available as >Daryl> microcode, which would be much slower than the optimized >Daryl> instructions but still faster than RISC implementations. >Daryl> Motorola seems to be doing exactly this with the 68040, ... >Are they, _really_ taking this approach? I ask because I don't know >either. >Daryl> I've seen 1.2-1.3 cyc/ins all over the place.. >Ditto for the 80486. (No flames, please:-) However, there are current >RISC processors that manage to average _less_ than 1 cycle per instruction. >(I've even heard of 1/2-1/3 Cycles Per Instruction peak performance. How >_do_ they do that?) It's quite easy, actually. If you know that the bus interface is going to be busy for a cycle, use that cycle to perform a "future" ALU operation. The 68020, even, had peak operations of 0 clock cycles. I have experimentally verified this. Not as a flame, but a comment, since the '040 has 2 internal busses (Harvard Architecture), and a separate ALU for operand address calculations, its PEAK operation rate is higher than the '486. The '486 does have a very smart pipeline, though. Both processors, however, still, ultimately, have to get the opcodes and operands from memory/disk, and this is where real differences in overall system performance are made. -- * Dan Taylor * The opinions expressed are my own, and in no way * * dlt@locus.com * reflect those of Locus Computing Corporation. *