Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!emory!hubcap!dawill From: dawill@hubcap.clemson.edu (david williams) Newsgroups: comp.sys.amiga.hardware Subject: Re: RISC Amiga WHat's RISC? Message-ID: <11656@hubcap.clemson.edu> Date: 16 Nov 90 10:57:04 GMT References: <39367@ut-emx.uucp> <15759@cbmvax.commodore.com> Organization: Clemson University, Clemson, SC Lines: 54 In article , Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips) writes: > >>>>> On 9 Nov 90 22:25:01 GMT, milamber@caen.engin.umich.edu (Daryl Scott Cantrell) said: > Daryl> RISC == Reduced Instruction Set Computing. > > Just a few months ago, I thought that also. (I was then a RISC basher, > BTW.) As it turns out, RISC is a misnomer. The cornerstone of RISC is > ruthless _quantitative_ analysis; features (instructions, cache, etc.) are > only added as they prove themselves _quantitatively_ (cost/performance) > when executing _real programs_. > > Merely reducing the instruction set doesn't necessarily buy you much. If > it did, we'd all be using 6502s with 50MHz clocks. "So why is it called > 'RISC'?" you ask. Beats me. Instruction set size is only one of many > variables, as is explained in H&P's book. Most RISC processors tend to have a rather large register set, to minimize the memory fetches required to carry out a given instruction sequence (more registers == less fetches to get intermediate results) 6502 fails miserably at this ... :-) [stuff deleted about CISC being able to speed up with RISC techniques] > > Daryl> Motorola seems to be doing exactly this with the 68040, ... > Are they, _really_ taking this approach? I ask because I don't know > either. Yes - Motorola made big claims about their new techniques to do this when they introduced the 68040. Note that a company called EDGE was making a RISC-like chip a little while back that ran 68000 code at an average rate of 1.4 cyc/ins a few years back... Big ASIC chip, I believe... > Daryl> I've seen 1.2-1.3 cyc/ins all over the place.. > > Ditto for the 80486. (No flames, please:-) However, there are current > RISC processors that manage to average _less_ than 1 cycle per instruction. > (I've even heard of 1/2-1/3 Cycles Per Instruction peak performance. How > _do_ they do that?) The Intel 860 and 960 chips achieve this sort of performance by having multiple computation units. I think there are *two* integer units, and a floating point unit. Carefull programing can have 3 instructions going on, one in each unit (of course, the I units would tend to complete instructions faster than the F unit can, so techniques have to balance the load carefully) Naturally, the IPU's and the FPU are pipelined, so that their average cycles are low. Pretty neat chip all around... Dave Williams dawill@hubcap.clemson.edu "Huh? What? Could you repeat the question?"