Path: utzoo!attcan!uunet!mcsun!ukc!dcl-cs!aber-cs!athene!pcg From: pcg@cs.aber.ac.uk (Piercarlo Grandi) Newsgroups: comp.sys.m88k Subject: Re: Tektronix shutdown & move away from 88k's?? (really, Apple rumor) Message-ID: Date: 10 Nov 90 20:40:55 GMT References: <1990Oct19.120218.9450@canterbury.ac.nz> <15497@hydra.gatech.EDU> <1990Oct31.180726.18797@unx.sas.com> <42775@mips.mips.COM> <42964@mips.mips.COM> Sender: pcg@aber-cs.UUCP Organization: Coleg Prifysgol Cymru Lines: 59 Nntp-Posting-Host: odin In-reply-to: crisp@mips.COM's message of 9 Nov 90 03:15:24 GMT On 9 Nov 90 03:15:24 GMT, crisp@mips.COM (Richard Crisp) said: crisp> From my perspective "factually correct" would mean that the crisp> essence of the story is true. The story as originally reported crisp> was that Moto would offer EPROM based, user re-microprogrammable crisp> 68000's. From how I had read the Byte story at the time that was not my understanding. A lot of time has passed, but my recollection (I do not keep copies of Byte that old) was that it would not have loadable or user changeable microcode, but that Motorola would offer the possibility to have custom instruction sets -- and I seem to remember that this most probably meant a different mask. I don't remember the EPROM thing; I guess that I would have been impressed by this detail, because the implications would have been really interesting. Or maybe I just read onchip ROM instead of EPROM. crisp> To me the essence of the story is that Moto planned to offer user crisp> microprogrammable 68k's. Whether it was done in EPROM or some crisp> other way, was insignificant. Again, my perception of the essence of the story was that Motorola planned to offer *customer* microprogrammed 68ks, that is in essence bespoke instruction sets, if you were prepared to pay. And they did this, even if IBM was presumably the only taker. The significance of the event was that they were prepared to change (within limits) their architecture, if you bought enough of their silicon, and this meant that they had designed the cip with that goal in mind. If they had put the microcode in EPROM we would have had the first microcomputer RISC as soon as somebody substituted the EPROM (assuming ti could be external) with a fast RAM cache... :-). Apart from this difference of interpretation, let's try to justify this article's presence in comp.sys.88k, by musing on this new chip's ability to support multiple instruction sets. Apparently (from a thread in comp.arch, and considering Sir Clive Sinclair's work on a very fast RISC) the way to go now is not to have ROM/EPROM microprogrammable chips, but RISC/VLIW chips that can emulate in "sw" higher level architectures. Does anybody know of object level translators or interpreted emulators or hybrids from/to the 88k architecture (e.g. like running MIPS code on a VAX)? How good is the 88k architecture, e.g. compared to the MIPS or SPARC or AMD 29k ones, as un UCODE, e.g. to emulate other RISC/CISC architectures, or as a target from them? Which you think are the easiest to emulate/translate with the 88k? -- Piercarlo Grandi | ARPA: pcg%uk.ac.aber.cs@nsfnet-relay.ac.uk Dept of CS, UCW Aberystwyth | UUCP: ...!mcsun!ukc!aber-cs!pcg Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk