Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!wuarchive!psuvax1!swatsun!swatsun!gessel From: gessel@carthage.cs.swarthmore.edu (Daniel Mark Gessel) Newsgroups: comp.sys.next Subject: Re: Overall speed Message-ID: Date: 13 Nov 90 20:31:58 GMT References: <7567@umd5.umd.edu> Sender: news@cs.swarthmore.edu Organization: Swarthmore College, Swarthmore Pa. Lines: 49 In-Reply-To: matthews@umd5.umd.edu's message of 13 Nov 90 14:17:02 GMT Nntp-Posting-Host: carthage In article <7567@umd5.umd.edu> matthews@umd5.umd.edu (Mike Matthews) writes: I would have done a Followup to this, but is-next does not have permission to post news, and I don't rn on umd5 here because it's usually loaded down way too much... Anyway, after reading all of this discussion about speeds of the SPARC 2 and all, and I have a question. The SPARC 2 is a RISC machine, right? So it's 28 MIPS is fast, but each instruction isn't doing all that much. But the NeXT's 15 MIPS is CISC architecture, so each instruction does a full command, so to speak. Assuming a CISC instruction is approximately equal to three or so (on average) RISC instructions... ? Am I missing something? I don't think so. There was a talk at swat here recently by the project leader (who's name I forget) of the 68040 processor. I've also read a little about the architecture (the guys talk was for engineering majors and was mostly about the process of designing a larger than 1M transistor chip). I haven't compared the two types of processors, and I'm just learning 68000 assembly for a compilers project, but my impression is that the above is correct. The integer pipeline is 6 stages, and my suspicion is that those stages can do quite a bit, although I don't know the equivalence to a RISC command. They did alot of tracings on 68000 systems, and the '040 has optimized instructions for the most common commands. The most often used instructions are executed one per cycle. Before I go on to create any wild rumors about CISC vs. RISC, anybody know where I could get user's manuals etc for the sparc chips? I'm no hardware expert, but I think I know enough (and if I don't, I know someone who does) to make a decent comparison. I could even go as far as trying to figure out certain kinds of functions and try to optimize the code on both processors, if people are really interested (and I find the time). Or maybe somebody has already done this sort of thing in the great RISC vs. CISC battle? Dan -- Daniel Mark Gessel Independent Consultant Internet: gessel@cs.swarthmore.edu My opinions are mine. (a -> a)