Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!samsung!emory!gatech!uflorida!haven!umd5!matthews
From: matthews@umd5.umd.edu (Mike Matthews)
Newsgroups: comp.sys.next
Subject: Overall speed
Message-ID: <7567@umd5.umd.edu>
Date: 13 Nov 90 14:17:02 GMT
Reply-To: matthews@is-next.umd.edu (Mike Matthews)
Organization: University of Maryland, College Park
Lines: 20

I would have done a Followup to this, but is-next does not have permission to
post news, and I don't rn on umd5 here because it's usually loaded down way
too much...

Anyway, after reading all of this discussion about speeds of the SPARC 2 and
all, and I have a question.

The SPARC 2 is a RISC machine, right?  So it's 28 MIPS is fast, but each
instruction isn't doing all that much.

But the NeXT's 15 MIPS is CISC architecture, so each instruction does a full
command, so to speak.  Assuming a CISC instruction is approximately equal to
three or so (on average) RISC instructions... ?

Am I missing something?


-- 
"The shortest distance between two points is under construction." - UMCP motto
   Mike Matthews (matthews@umd5.umd.edu, bitnet matthews@umdd)