Path: utzoo!attcan!uunet!nih-csl!lhc!adm!cmcl2!yale!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!caen!gilgalad
From: gilgalad@caen.engin.umich.edu (Ralph Seguin)
Newsgroups: comp.sys.next
Subject: Re: Overall speed
Message-ID: <1990Nov15.141016.16319@engin.umich.edu>
Date: 15 Nov 90 14:10:16 GMT
References: <7567@umd5.umd.edu> <643@storm.UUCP>
Sender: news@engin.umich.edu (CAEN Netnews)
Organization: University of Michigan Engineering, Ann Arbor
Lines: 19

>In article <7567@umd5.umd.edu> matthews@is-next.umd.edu (Mike Matthews) writes:
>>The SPARC 2 is a RISC machine, right?  So it's 28 MIPS is fast, but each
>>instruction isn't doing all that much.

The POWER (Performance Optimized With Enhanced RISC) chips used in the RS/6000s
have several execution units.  Quite a bit can be done by each instruction.
They use a different senses of the word RISC.  What they mean is reduce the
number of cycles per instruction.  On the 320, they were averaging LESS
than 1 cycle per instruction.
This is nonsense.  The RS/6000s SCREAM.  I have been using them for quite some
time now.  They give SPECmarks which kill every other machine at that price
level.
There is, of course, the matter of software.  AIX is still buggy.

			See ya, Ralph

Ralph Seguin			gilgalad@dip.eecs.umich.edu
536 South Forest Apt. #915	gilgalad@caen.engin.umich.edu
Ann Arbor, MI 48104		(313) 662-4805