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From: ellis@ultra.dec.com (David Ellis 15-Nov-1990 0915)
Newsgroups: comp.unix.programmer
Subject: Makefiles -- .c and .h
Message-ID: <9011151442.AA02010@decpa.pa.dec.com>
Date: 15 Nov 90 14:43:00 GMT
Sender: daemon@wrl.dec.com (System programs)
Organization: Digital Equipment Corporation
Lines: 23
To: comp.unix.programmer.usenet

Consider a Makefile for an executable built from a large number of .o files, 
each separately compiled from a .c file.

If we use a single .c.o rule for compiling all the source files, then it 
seems that a change in a .h file that is #include'd in a .c file will
not be picked up by Make to automatically force recompilation of the .c file.

One workaround is to replace the single .c.o rule with a collection of rules, 
one for each .o file, listing the dependencies on the .h files #include'd in
the corresponding .c file.  But this is a lot of writing, and if we change
the "#include" lines in any .c file, we have to update the Makefile with the
corresponding change.

Is there a simpler way?

----
David  J  Ellis
Digital Equipment Corporation, Secure Systems Group 
Mailstop LTN1-1/D07
295 Foster Street, Littleton MA 01460
(508) 486-6157
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Internet: ellis@ultra.enet.dec.com