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From: srh@tridom.uucp (Steve Harmon)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Message-ID: <1990Nov9.143418.14746@tridom.uucp>
Date: 9 Nov 90 14:34:18 GMT
Reply-To: srh@tridom.UUCP (Steve Harmon)
Organization: Devient Designs  Atlanta, GA.
Lines: 51

>>>>In an old (autumn 1987) issue of BYTE they were testing 12 exTended memory 
>>>>expansion board. They measured and published figures for how much each board
>>>>slowed down the system, just by being installed... They even got different
>>>>figures for each board... They claimed that this slowdown was due to the extra
>>>>time it takes to refresh the extra RAM.
>>>>
>>>Quite possibly because the AT Bus is running at 8MHz, so refreshing that DRAM
>>>takes longer than refreshing DRAM on the motherboard which can be refreshed
>>>at a greater speed.
>>>
>> The problem here stems from the fact that memory refreshing is usually
>> carried out through DMA cycles.  The implications of this are that the
>> ....
>> 
>> The conclusion is that for more memory, there will be more refresh necessary,
>> and thus more DMA cycles necessary, and more time where the processor must
>> release the bus to the memory controller.  I hope this clears things up.
>
>  It depends on how the refresh is implemented, on whether or not you'll
>find a performance difference.  A DMA channel is used on PCs (unfortunately)
>to refresh the DRAM.  Each chip has to have each row address read or written
>every 4ms in order to refresh it.  The DMA controller refreshes by moving
>a block of memory to itself.  If you have a single bank of DRAM (1 bank
>being the number of chips necessary for one word width on the data bus)
>then one block move will have to be done.  If
>you expand the chips themselves, say from 1Mbyte to 4Mbyte chips, there
>shouldn't be any impact on refresh.  If you expand memory by adding more
>banks of DRAM, whether on the motherboard or on an aboveboard memory card,
>the DMA controller has to hit more addresses so that each chip is refreshed,
>and therefore has to do more block moves in the same 4ms.
>
>  In a *real* refreshing scheme, you would refresh all banks at the same
>time, or if you want to get tricky, stagger the bank refresh so that the
>refresh of 1 bank coincides with a memory access to another bank.

    Hmmm...  My memory is a little fuzzy about the PC design (or lack of)
so I'm sure someone will be kind enough to correct me if I'm way off base.
As I remember it, channel 0 of the DMA controller is used as nothing more
than an address generator.  It periodically aquires the bus, asserts an
address and starts a transfer cycle which is signaled as a refresh cycle
(via -BREFRESH I believe).  The amout of memory that is being refreshed is
not significant to the refresh scheme.  Although, memory placed on the
expansion bus will probably be subject to wait states.  All in all, the only
reason that I see for increased refresh time for above board memory would be
due to the added wait states.

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