Path: utzoo!attcan!uunet!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!ncar!gatech!mcnc!ncsuvx!news From: dsh@csl36h.csl.ncsu.edu (Doug Holtsinger) Newsgroups: sci.electronics Subject: Re: Analog and Digital Design Message-ID: <1990Nov12.221433.15857@ncsuvx.ncsu.edu> Date: 12 Nov 90 22:14:33 GMT References: <11242.2730bfd5@ecs.umass.edu> <1990Nov2.223926.26095@ameristar> <47O.029T03cv01@JUTS.ccc.amdahl.com> <1990Nov12.045429.20147@ncsuvx.ncsu.edu> <32696@netnews.upenn.edu> Reply-To: dsh@csl36h.csl.ncsu.edu.UUCP (Doug Holtsinger) Distribution: na Organization: North Carolina State University Lines: 26 In article touch@dsl.cis.upenn.edu (Joe Touch) writes: >In article dsh@csl36h.csl.ncsu.edu.UUCP (Doug Holtsinger) writes: > >>Digital design is getting to be much more than just ones and zeros. >>Just try designing a digital board to run at > 30 Mhz without analyzing >>board trace delays, or dealing with reflection problems, etc.. > >You don't have to get into analog problems to require 'the right >approach'. I've seen boards built to 150 Mhz without board trace >delay or reflection requiring analog analyis. Well, the original poster discussed the 'right approach' as it pertains to analog design, not digital design. Your experience at 150 Mhz is not anything like mine at lower frequencies. Sure, you could build a couple of boards with lazy timing, and if it works then you declare that the design is correct. That's not the way it works in the real world - where getting competitive, reliable designs into _mass production_ requires such analysis. My original point was that digital (board) designers who fail to understand analog issues are placing themselves at a severe disadvantage. > >Joe Touch >touch@cis.upenn.edu ---------------- dsh@csl.ncsu.edu