Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!njin!princeton!udel!wuarchive!uunet!motcid!koch
From: koch@motcid.UUCP (Clifton Koch)
Newsgroups: sci.electronics
Subject: Re: Refreshing DRAM
Message-ID: <5270@navy22.UUCP>
Date: 14 Nov 90 22:02:49 GMT
References: <1990Nov9.143418.14746@tridom.uucp>
Organization: Motorola Inc., Cellular Infrastructure Div., Arlington Heights, IL
Lines: 17

->     Hmmm...  My memory is a little fuzzy about the PC design (or lack of)
-> so I'm sure someone will be kind enough to correct me if I'm way off base.
-> As I remember it, channel 0 of the DMA controller is used as nothing more
-> than an address generator.  It periodically aquires the bus, asserts an
-> address and starts a transfer cycle which is signaled as a refresh cycle
-> (via -BREFRESH I believe).  The amout of memory that is being refreshed is
-> not significant to the refresh scheme.  Although, memory placed on the
-> expansion bus will probably be subject to wait states.  All in all, the only
-> reason that I see for increased refresh time for above board memory would be
-> due to the added wait states.

  Yup, I had forgotten about the refresh signal on the PC bus, so I was
wrong (oh, well, it had to happen someday :-).
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