Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!think.com!mintaka!spdcc!iecc!Postmaster
From: johnl@iecc.cambridge.ma.us (John R. Levine)
Newsgroups: comp.arch
Subject: Re: True 46 Bit Addressing with 586?
Message-ID: <9011201540.AA03345@iecc.cambridge.ma.us>
Date: 20 Nov 90 20:40:25 GMT
References: <21691@well.sf.ca.us>
Sender: Postmaster@iecc.cambridge.ma.us
Organization: I.E.C.C., Cambridge MA 02238
Lines: 39
In-Reply-To: <8833@scolex.sco.COM>

In article <8833@scolex.sco.COM> you write:
>In article <21691@well.sf.ca.us> feustel@well.sf.ca.us (David Alan Feustel) writes:
>>[The 386 and 486 don't really have the alleged 46 bit addressing because]
>> the mapping of all segments into the single 32 bit virtual address space
>>... imposes the restriction the sum of the length of the code, data and
>>stack segments must be less than or equal to 4 gigabytes ...
>
>Uhm, no, it doesn't.  Take a look at how memory management is done on the
>*86 again, and you'll see a couple of different ways you can do it.

Really, it does.  The 386 has six segment registers offering up to six
simultaneously addressable segments.  All six addressable segments must be
mapped into the 32 bit linear address space (loading a segment register
fails if you try to load a not-present segment, and the operating system has
to map it before the process can continue.)  Remember that the paging
happens underneath the linear space -- a segment is either mapped into the
linear space entirely or not at all.  In practice this either means that you
restrict each segment to 29 bits, so you can map them by fiddling page
directories and reserve 1/8 of the linear space for each segment, or more
commonly require that the entire set of mappable segments map into 32 bits.

Also remember that if you have an operating system, it has to be mapped into
the linear space as well so it can take traps and system calls.

Even if a scheme that maps segments in and out works in theory, it is likely
to have dreadful performance since traps and page table manipulation are slow.

>Also, I don't believe you can get 46-bit addressing completely.  The chip
>can have a total of 46-bit virtual addresses, but some of those are going to
>be for ring 0, some for ring 1, etc.

The segment number is 16 bits, but two of those are the ring number, leaving
14 segment number bits plus 32 bit intrasegment addresses makes 46.  One
might say it's more meaningful to say 45 bits per process plus a 45 bit
global address space (another segment bit is the local/global bit) but
that's a relative nit.

Regards,
John Levine, johnl@iecc.cambridge.ma.us, {spdcc|ima|world}!iecc!johnl