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From: rabbit42@matt.ksu.ksu.edu (Bruce Corwin McLaren)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: npn tranistors in magic
Keywords: npn transistors, magic, vlsi cad
Message-ID: <1990Nov19.191540.19052@maverick.ksu.ksu.edu>
Date: 19 Nov 90 19:15:40 GMT
Sender: news@maverick.ksu.ksu.edu (The News Guru)
Organization: Kansas State University
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Has anyone successfully done npn transistors in magic using
the new scmos tech file (the low_noise_analog process from mosis) ?

How are they arranged?
The design rules seem to say that the emitter must be overlapped 
by the base but the collector cannot touch the base.

Also, are the resulting transistors extractable?

Sorry for the simplsitic questions, but I am getting a might confused.

Bruce McLaren
mclaren@eesun1.eece.ksu.edu  or
rabbit42@matt.ksu.ksu.edu    or
rabbit42@ksuvm