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From: sllu@jenny.isi.edu (Shih-Lien Lu)
Newsgroups: comp.lsi.cad,comp.lsi
Subject: Re: npn tranistors in magic
Keywords: npn transistors, magic, vlsi cad
Message-ID: <15747@venera.isi.edu>
Date: 20 Nov 90 00:55:23 GMT
References: <1990Nov19.191540.19052@maverick.ksu.ksu.edu>
Sender: news@isi.edu
Reply-To: sllu@jenny.isi.edu.UUCP (Shih-Lien Lu)
Organization: USC-Information Sciences Institute
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>Has anyone successfully done npn transistors in magic using
>the new scmos tech file (the low_noise_analog process from mosis) ?

Yes we have. We may be able to arrange public ftp of an npn transistor.

>How are they arranged?
>The design rules seem to say that the emitter must be overlapped 
>by the base but the collector cannot touch the base.

Yes. The emitter is covered by the pbase layer while colloect contact
cannot touch the pbase. The nwell is the collector and the collect contact
ties the collect to metal.

>Also, are the resulting transistors extractable?

Not right now. In the future, MOSIS will offer post-processing program
that will allow user to do auto-extraction of npn transistors.

>Sorry for the simplsitic questions, but I am getting a might confused.

We apologize for any confusion resulted for our messages,documents and
annocements. I have a new doc. on the new SCMOS technology file.
You may request a hard copy by sending a message to MOSIS.

Shih-Lien Lu
for MOSIS